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48257490be
Fix the following Coverity Defects: clk_mon_tu104.c : Out-of-bounds write clk_mon_tu104.c : Out-of-bounds read clk_mon_tu104.c : Out-of-bounds access Fix the following CERT-C Defects: clk_mon_tu104.c : CERT STR31-C For fixing an older Coverity defect, we had changed datatype of domain mask from u32 to unsigned long. This thing generates another issue. bit_pos range changes from [0,32) to [0,64). Changing CLK_CLOCK_MON_DOMAIN_COUNT from 0x32U to 0x40U solves the issue. CID 10138023 CID 10138024 CID 10138025 CID 518885 CID 518887 CID 518890 Bug 3460991 Bug 3512546 Signed-off-by: Jinesh Parakh <jparakh@nvidia.com> Change-Id: I2a4853d87d7bb316db3de56ef34a039bf02486d7 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2728545 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>