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08aaaecc61
Access to falcon's EMEM has to be synchronized to ensure atomic access to EMEM control and data registers. Add this locking. Not all falcons support EMEM hence handle mutex based on the enabled flag emem_supported that is set only for TU104 currently. JIRA NVGPU-1993 Change-Id: Idaedfb564ea0068d4690a2717d7983eb2384a69f Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2030618 GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
87 lines
2.7 KiB
C
87 lines
2.7 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/falcon.h>
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#include "falcon_sw_gk20a.h"
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#include "falcon_sw_gv100.h"
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#include "falcon_sw_tu104.h"
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void tu104_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn)
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{
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struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops =
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&flcn->flcn_engine_dep_ops;
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struct gk20a *g = flcn->g;
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gk20a_falcon_engine_dependency_ops(flcn);
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switch (flcn->flcn_id) {
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case FALCON_ID_SEC2:
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flcn_eng_dep_ops->reset_eng = g->ops.sec2.sec2_reset;
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flcn_eng_dep_ops->copy_to_emem = g->ops.sec2.sec2_copy_to_emem;
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flcn_eng_dep_ops->copy_from_emem =
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g->ops.sec2.sec2_copy_from_emem;
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break;
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default:
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flcn_eng_dep_ops->reset_eng = NULL;
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break;
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}
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}
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void tu104_falcon_sw_init(struct nvgpu_falcon *flcn)
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{
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struct gk20a *g = flcn->g;
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switch (flcn->flcn_id) {
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case FALCON_ID_SEC2:
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flcn->flcn_base = g->ops.sec2.falcon_base_addr();
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flcn->is_falcon_supported = true;
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flcn->is_interrupt_enabled = true;
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flcn->emem_supported = true;
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break;
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case FALCON_ID_NVDEC:
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flcn->flcn_base = g->ops.nvdec.falcon_base_addr();
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flcn->is_falcon_supported = true;
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flcn->is_interrupt_enabled = true;
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break;
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default:
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/*
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* set false to inherit falcon support
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* from previous chips HAL
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*/
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flcn->is_falcon_supported = false;
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break;
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}
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if (flcn->is_falcon_supported) {
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tu104_falcon_engine_dependency_ops(flcn);
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} else {
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/*
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* Forward call to previous chip's SW init
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* to fetch info for requested
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* falcon as no changes between
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* current & previous chips.
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*/
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gv100_falcon_sw_init(flcn);
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}
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}
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