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97d65cb60d
MISRA Rule-17.7 requires the return value of all functions to be used. Fix is either to use the return value or change the function to return void. This patch contains fixes for all 17.7 violations in the following units: - nvgpu.hal.bus - nvgpu.hal.fb - nvgpu.hal.fifo - nvgpu.hal.gr JIRA NVGPU-3153 Change-Id: Iac9477ee7c36a0f2f8840e178dc5418e600f9c84 Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2100652 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
74 lines
2.4 KiB
C
74 lines
2.4 KiB
C
/*
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* GM20B MMU
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*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/timers.h>
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#include <nvgpu/mm.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include "bus_gm20b.h"
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#include <nvgpu/hw/gm20b/hw_bus_gm20b.h>
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int gm20b_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst)
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{
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struct nvgpu_timeout timeout;
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int err = 0;
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u64 iova = nvgpu_inst_block_addr(g, bar1_inst);
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u32 ptr_v = (u32)(iova >> bus_bar1_block_ptr_shift_v());
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nvgpu_log_info(g, "bar1 inst block ptr: 0x%08x", ptr_v);
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gk20a_writel(g, bus_bar1_block_r(),
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nvgpu_aperture_mask(g, bar1_inst,
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bus_bar1_block_target_sys_mem_ncoh_f(),
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bus_bar1_block_target_sys_mem_coh_f(),
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bus_bar1_block_target_vid_mem_f()) |
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bus_bar1_block_mode_virtual_f() |
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bus_bar1_block_ptr_f(ptr_v));
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err = nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER);
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if (err != 0) {
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nvgpu_err(g, "nvgpu_timeout_init failed err=%d", err);
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return err;
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}
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do {
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u32 val = gk20a_readl(g, bus_bind_status_r());
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u32 pending = bus_bind_status_bar1_pending_v(val);
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u32 outstanding = bus_bind_status_bar1_outstanding_v(val);
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if (pending == 0U && outstanding == 0U) {
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break;
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}
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nvgpu_udelay(5);
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} while (nvgpu_timeout_expired(&timeout) == 0);
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if (nvgpu_timeout_peek_expired(&timeout) != 0) {
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err = -EINVAL;
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}
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return err;
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}
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