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47dc0b9ebd
Moved the channel HAL files from common/fifo/ to hal/fifo Jira NVGPU-3248 Change-Id: Ibb85b7c0e71422dbd774a518e4f0bba0b97ef807 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2123399 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
125 lines
3.6 KiB
C
125 lines
3.6 KiB
C
/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/channel.h>
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#include <nvgpu/log.h>
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#include <nvgpu/atomic.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include "channel_gk20a.h"
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#include "channel_gv11b.h"
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#include <nvgpu/hw/gv11b/hw_ccsr_gv11b.h>
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void gv11b_channel_unbind(struct nvgpu_channel *ch)
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{
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struct gk20a *g = ch->g;
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nvgpu_log_fn(g, " ");
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if (nvgpu_atomic_cmpxchg(&ch->bound, (int)true, (int)false) != 0) {
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gk20a_writel(g, ccsr_channel_inst_r(ch->chid),
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ccsr_channel_inst_ptr_f(0) |
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ccsr_channel_inst_bind_false_f());
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gk20a_writel(g, ccsr_channel_r(ch->chid),
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ccsr_channel_enable_clr_true_f() |
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ccsr_channel_pbdma_faulted_reset_f() |
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ccsr_channel_eng_faulted_reset_f());
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}
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}
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u32 gv11b_channel_count(struct gk20a *g)
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{
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return ccsr_channel__size_1_v();
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}
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void gv11b_channel_read_state(struct gk20a *g, struct nvgpu_channel *ch,
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struct nvgpu_channel_hw_state *state)
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{
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u32 reg = gk20a_readl(g, ccsr_channel_r(ch->chid));
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gk20a_channel_read_state(g, ch, state);
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state->eng_faulted = ccsr_channel_eng_faulted_v(reg) ==
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ccsr_channel_eng_faulted_true_v();
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}
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void gv11b_channel_reset_faulted(struct gk20a *g, struct nvgpu_channel *ch,
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bool eng, bool pbdma)
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{
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u32 reg = gk20a_readl(g, ccsr_channel_r(ch->chid));
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if (eng) {
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reg |= ccsr_channel_eng_faulted_reset_f();
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}
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if (pbdma) {
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reg |= ccsr_channel_pbdma_faulted_reset_f();
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}
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gk20a_writel(g, ccsr_channel_r(ch->chid), reg);
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}
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void gv11b_channel_debug_dump(struct gk20a *g,
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struct nvgpu_debug_context *o,
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struct nvgpu_channel_dump_info *info)
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{
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gk20a_debug_output(o, "%d-%s, TSG: %u, pid %d, refs: %d%s: ",
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info->chid,
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g->name,
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info->tsgid,
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info->pid,
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info->refs,
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info->deterministic ? ", deterministic" : "");
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gk20a_debug_output(o, "channel status: %s in use %s %s\n",
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info->hw_state.enabled ? "" : "not",
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info->hw_state.status_string,
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info->hw_state.busy ? "busy" : "not busy");
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gk20a_debug_output(o,
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"RAMFC : TOP: %016llx PUT: %016llx GET: %016llx "
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"FETCH: %016llx\n"
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"HEADER: %08x COUNT: %08x\n"
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"SEMAPHORE: addr %016llx\n"
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"payload %016llx execute %08x\n",
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info->inst.pb_top_level_get,
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info->inst.pb_put,
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info->inst.pb_get,
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info->inst.pb_fetch,
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info->inst.pb_header,
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info->inst.pb_count,
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info->inst.sem_addr,
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info->inst.sem_payload,
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info->inst.sem_execute);
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if (info->sema.addr != 0ULL) {
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gk20a_debug_output(o, "SEMA STATE: value: 0x%08x "
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"next_val: 0x%08x addr: 0x%010llx\n",
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info->sema.value,
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info->sema.next,
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info->sema.addr);
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}
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gk20a_debug_output(o, "\n");
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}
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