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cfb4ff0bfb
Rename struct fifo_gk20a -> nvgpu_fifo JIRA NVGPU-2012 Change-Id: Ifb5854592c88894ecd830da092ada27c7f05380d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2109625 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
103 lines
3.0 KiB
C
103 lines
3.0 KiB
C
/*
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* GV11B fifo
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*
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* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/log.h>
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#include <nvgpu/soc.h>
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#include <nvgpu/io.h>
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#include <nvgpu/fifo.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/unit.h>
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#include <nvgpu/power_features/cg.h>
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#include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
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#include "fifo_gv11b.h"
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int gv11b_init_fifo_reset_enable_hw(struct gk20a *g)
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{
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u32 timeout;
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nvgpu_log_fn(g, " ");
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/* enable pmc pfifo */
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g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_FIFO));
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nvgpu_cg_slcg_ce2_load_enable(g);
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nvgpu_cg_slcg_fifo_load_enable(g);
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nvgpu_cg_blcg_fifo_load_enable(g);
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timeout = nvgpu_readl(g, fifo_fb_timeout_r());
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nvgpu_log_info(g, "fifo_fb_timeout reg val = 0x%08x", timeout);
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if (!nvgpu_platform_is_silicon(g)) {
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timeout = set_field(timeout, fifo_fb_timeout_period_m(),
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fifo_fb_timeout_period_max_f());
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timeout = set_field(timeout, fifo_fb_timeout_detection_m(),
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fifo_fb_timeout_detection_disabled_f());
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nvgpu_log_info(g, "new fifo_fb_timeout reg val = 0x%08x",
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timeout);
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nvgpu_writel(g, fifo_fb_timeout_r(), timeout);
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}
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g->ops.pbdma.setup_hw(g);
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g->ops.fifo.intr_0_enable(g, true);
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g->ops.fifo.intr_1_enable(g, true);
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nvgpu_log_fn(g, "done");
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return 0;
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}
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int gv11b_init_fifo_setup_hw(struct gk20a *g)
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{
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struct nvgpu_fifo *f = &g->fifo;
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f->max_subctx_count = g->ops.gr.init.get_max_subctx_count();
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/* configure userd writeback timer */
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nvgpu_writel(g, fifo_userd_writeback_r(),
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fifo_userd_writeback_timer_f(
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fifo_userd_writeback_timer_100us_v()));
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return 0;
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}
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u32 gv11b_fifo_mmu_fault_id_to_pbdma_id(struct gk20a *g, u32 mmu_fault_id)
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{
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u32 num_pbdma, reg_val, fault_id_pbdma0;
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reg_val = nvgpu_readl(g, fifo_cfg0_r());
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num_pbdma = fifo_cfg0_num_pbdma_v(reg_val);
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fault_id_pbdma0 = fifo_cfg0_pbdma_fault_id_v(reg_val);
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if (mmu_fault_id >= fault_id_pbdma0 &&
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mmu_fault_id <= fault_id_pbdma0 + num_pbdma - 1U) {
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return mmu_fault_id - fault_id_pbdma0;
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}
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return INVAL_ID;
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}
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