mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-25 02:52:51 +03:00
05ed37ae3a
This patch does the following:
(1) Removes the usage of hw headers in SDL unit. For this purpose, it moves
the initialization required for errors that can be injected using hw
support, error injection function. Further, it passes the required
information to SDL via hal layers.
(2) Renames (i) PWR as PMU, (ii) nvgpu_report_ecc_parity_err to
nvgpu_report_ecc_err.
Jira NVGPU-3235
Change-Id: I69290af78c09fbb5b792058e7bc6cc8b6ba340c9
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112837
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
496 lines
14 KiB
C
496 lines
14 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/io.h>
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#include <nvgpu/ecc.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
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#include "ecc_gv11b.h"
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static struct nvgpu_hw_err_inject_info fecs_ecc_err_desc[] = {
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NVGPU_ECC_ERR("falcon_imem_ecc_corrected",
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gv11b_gr_intr_inject_fecs_ecc_error,
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gr_fecs_falcon_ecc_control_r,
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gr_fecs_falcon_ecc_control_inject_corrected_err_f),
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NVGPU_ECC_ERR("falcon_imem_ecc_uncorrected",
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gv11b_gr_intr_inject_fecs_ecc_error,
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gr_fecs_falcon_ecc_control_r,
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gr_fecs_falcon_ecc_control_inject_uncorrected_err_f),
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};
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static struct nvgpu_hw_err_inject_info_desc fecs_err_desc;
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struct nvgpu_hw_err_inject_info_desc *
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gv11b_gr_intr_get_fecs_err_desc(struct gk20a *g)
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{
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fecs_err_desc.info_ptr = fecs_ecc_err_desc;
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fecs_err_desc.info_size = nvgpu_safe_cast_u64_to_u32(
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sizeof(fecs_ecc_err_desc) /
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sizeof(struct nvgpu_hw_err_inject_info));
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return &fecs_err_desc;
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}
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int gv11b_gr_intr_inject_fecs_ecc_error(struct gk20a *g,
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struct nvgpu_hw_err_inject_info *err, u32 error_info)
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{
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nvgpu_info(g, "Injecting FECS fault %s", err->name);
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nvgpu_writel(g, err->get_reg_addr(), err->get_reg_val(1U));
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return 0;
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}
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static struct nvgpu_hw_err_inject_info gpccs_ecc_err_desc[] = {
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NVGPU_ECC_ERR("falcon_imem_ecc_corrected",
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gv11b_gr_intr_inject_gpccs_ecc_error,
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gr_gpccs_falcon_ecc_control_r,
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gr_gpccs_falcon_ecc_control_inject_corrected_err_f),
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NVGPU_ECC_ERR("falcon_imem_ecc_uncorrected",
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gv11b_gr_intr_inject_gpccs_ecc_error,
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gr_gpccs_falcon_ecc_control_r,
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gr_gpccs_falcon_ecc_control_inject_uncorrected_err_f),
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};
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static struct nvgpu_hw_err_inject_info_desc gpccs_err_desc;
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struct nvgpu_hw_err_inject_info_desc *
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gv11b_gr_intr_get_gpccs_err_desc(struct gk20a *g)
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{
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gpccs_err_desc.info_ptr = gpccs_ecc_err_desc;
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gpccs_err_desc.info_size = nvgpu_safe_cast_u64_to_u32(
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sizeof(gpccs_ecc_err_desc) /
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sizeof(struct nvgpu_hw_err_inject_info));
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return &gpccs_err_desc;
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}
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int gv11b_gr_intr_inject_gpccs_ecc_error(struct gk20a *g,
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struct nvgpu_hw_err_inject_info *err, u32 error_info)
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{
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unsigned int gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
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unsigned int gpc = (error_info & 0xFFU);
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unsigned int reg_addr = err->get_reg_addr() + gpc * gpc_stride;
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nvgpu_info(g, "Injecting GPCCS fault %s for gpc: %d", err->name, gpc);
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nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
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return 0;
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}
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static struct nvgpu_hw_err_inject_info sm_ecc_err_desc[] = {
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NVGPU_ECC_ERR("l1_tag_ecc_corrected",
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gv11b_gr_intr_inject_sm_ecc_error,
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gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_r,
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gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_inject_corrected_err_f),
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NVGPU_ECC_ERR("l1_tag_ecc_uncorrected",
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gv11b_gr_intr_inject_sm_ecc_error,
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gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_r,
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gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_inject_uncorrected_err_f),
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NVGPU_ECC_ERR("cbu_ecc_uncorrected",
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gv11b_gr_intr_inject_sm_ecc_error,
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gr_pri_gpc0_tpc0_sm_cbu_ecc_control_r,
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gr_pri_gpc0_tpc0_sm_cbu_ecc_control_inject_uncorrected_err_f),
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NVGPU_ECC_ERR("lrf_ecc_uncorrected",
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gv11b_gr_intr_inject_sm_ecc_error,
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gr_pri_gpc0_tpc0_sm_lrf_ecc_control_r,
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gr_pri_gpc0_tpc0_sm_lrf_ecc_control_inject_uncorrected_err_f),
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NVGPU_ECC_ERR("l1_data_ecc_uncorrected",
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gv11b_gr_intr_inject_sm_ecc_error,
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gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_r,
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gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_inject_uncorrected_err_f),
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NVGPU_ECC_ERR("icache_l0_data_ecc_uncorrected",
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gv11b_gr_intr_inject_sm_ecc_error,
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gr_pri_gpc0_tpc0_sm_icache_ecc_control_r,
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gr_pri_gpc0_tpc0_sm_icache_ecc_control_inject_uncorrected_err_f),
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};
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static struct nvgpu_hw_err_inject_info_desc sm_err_desc;
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struct nvgpu_hw_err_inject_info_desc *
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gv11b_gr_intr_get_sm_err_desc(struct gk20a *g)
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{
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sm_err_desc.info_ptr = sm_ecc_err_desc;
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sm_err_desc.info_size = nvgpu_safe_cast_u64_to_u32(
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sizeof(sm_ecc_err_desc) /
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sizeof(struct nvgpu_hw_err_inject_info));
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return &sm_err_desc;
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}
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int gv11b_gr_intr_inject_sm_ecc_error(struct gk20a *g,
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struct nvgpu_hw_err_inject_info *err,
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u32 error_info)
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{
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unsigned int gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
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unsigned int tpc_stride =
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nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
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unsigned int gpc = (error_info & 0xFF00U) >> 8U;
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unsigned int tpc = (error_info & 0xFFU);
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unsigned int reg_addr = err->get_reg_addr() + gpc * gpc_stride
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+ tpc * tpc_stride;
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nvgpu_info(g, "Injecting SM fault %s for gpc: %d, tpc: %d",
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err->name, gpc, tpc);
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nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
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return 0;
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}
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static struct nvgpu_hw_err_inject_info mmu_ecc_err_desc[] = {
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NVGPU_ECC_ERR("l1tlb_sa_data_ecc_uncorrected",
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gv11b_gr_intr_inject_mmu_ecc_error,
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gr_gpc0_mmu_l1tlb_ecc_control_r,
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gr_gpc0_mmu_l1tlb_ecc_control_inject_uncorrected_err_f),
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};
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static struct nvgpu_hw_err_inject_info_desc mmu_err_desc;
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struct nvgpu_hw_err_inject_info_desc *
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gv11b_gr_intr_get_mmu_err_desc(struct gk20a *g)
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{
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mmu_err_desc.info_ptr = mmu_ecc_err_desc;
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mmu_err_desc.info_size = nvgpu_safe_cast_u64_to_u32(
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sizeof(mmu_ecc_err_desc) /
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sizeof(struct nvgpu_hw_err_inject_info));
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return &mmu_err_desc;
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}
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int gv11b_gr_intr_inject_mmu_ecc_error(struct gk20a *g,
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struct nvgpu_hw_err_inject_info *err, u32 error_info)
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{
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unsigned int gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
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unsigned int gpc = (error_info & 0xFFU);
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unsigned int reg_addr = err->get_reg_addr() + gpc * gpc_stride;
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nvgpu_info(g, "Injecting MMU fault %s for gpc: %d", err->name, gpc);
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nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
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return 0;
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}
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static struct nvgpu_hw_err_inject_info gcc_ecc_err_desc[] = {
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NVGPU_ECC_ERR("l15_ecc_uncorrected",
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gv11b_gr_intr_inject_gcc_ecc_error,
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gr_pri_gpc0_gcc_l15_ecc_control_r,
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gr_pri_gpc0_gcc_l15_ecc_control_inject_uncorrected_err_f),
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};
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static struct nvgpu_hw_err_inject_info_desc gcc_err_desc;
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struct nvgpu_hw_err_inject_info_desc *
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gv11b_gr_intr_get_gcc_err_desc(struct gk20a *g)
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{
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gcc_err_desc.info_ptr = gcc_ecc_err_desc;
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gcc_err_desc.info_size = nvgpu_safe_cast_u64_to_u32(
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sizeof(gcc_ecc_err_desc) /
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sizeof(struct nvgpu_hw_err_inject_info));
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return &gcc_err_desc;
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}
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int gv11b_gr_intr_inject_gcc_ecc_error(struct gk20a *g,
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struct nvgpu_hw_err_inject_info *err, u32 error_info)
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{
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unsigned int gpc_stride = nvgpu_get_litter_value(g,
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GPU_LIT_GPC_STRIDE);
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unsigned int gpc = (error_info & 0xFFU);
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unsigned int reg_addr = err->get_reg_addr()
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+ gpc * gpc_stride;
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nvgpu_info(g, "Injecting GCC fault %s for gpc: %d", err->name, gpc);
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nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
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return 0;
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}
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void gv11b_ecc_detect_enabled_units(struct gk20a *g)
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{
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bool opt_ecc_en = g->ops.fuse.is_opt_ecc_enable(g);
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bool opt_feature_fuses_override_disable =
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g->ops.fuse.is_opt_feature_override_disable(g);
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u32 fecs_feature_override_ecc =
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nvgpu_readl(g,
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gr_fecs_feature_override_ecc_r());
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if (opt_feature_fuses_override_disable) {
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if (opt_ecc_en) {
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nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_LRF, true);
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nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_L1_DATA, true);
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nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_L1_TAG, true);
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nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_ICACHE, true);
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nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true);
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nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_CBU, true);
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}
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} else {
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/* SM LRF */
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if (gr_fecs_feature_override_ecc_sm_lrf_override_v(
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fecs_feature_override_ecc) == 1U) {
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if (gr_fecs_feature_override_ecc_sm_lrf_v(
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fecs_feature_override_ecc) == 1U) {
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nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_LRF, true);
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}
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} else {
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if (opt_ecc_en) {
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nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_LRF, true);
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}
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}
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/* SM L1 DATA*/
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if (gr_fecs_feature_override_ecc_sm_l1_data_override_v(
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fecs_feature_override_ecc) == 1U) {
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if (gr_fecs_feature_override_ecc_sm_l1_data_v(
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fecs_feature_override_ecc) == 1U) {
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nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_L1_DATA, true);
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}
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} else {
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if (opt_ecc_en) {
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nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_L1_DATA, true);
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}
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}
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/* SM L1 TAG*/
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if (gr_fecs_feature_override_ecc_sm_l1_tag_override_v(
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fecs_feature_override_ecc) == 1U) {
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if (gr_fecs_feature_override_ecc_sm_l1_tag_v(
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fecs_feature_override_ecc) == 1U) {
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nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_L1_TAG, true);
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}
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} else {
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if (opt_ecc_en) {
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nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_L1_TAG, true);
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}
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}
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/* SM ICACHE*/
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if ((gr_fecs_feature_override_ecc_1_sm_l0_icache_override_v(
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fecs_feature_override_ecc) == 1U) &&
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(gr_fecs_feature_override_ecc_1_sm_l1_icache_override_v(
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fecs_feature_override_ecc) == 1U)) {
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if ((gr_fecs_feature_override_ecc_1_sm_l0_icache_v(
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fecs_feature_override_ecc) == 1U) &&
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(gr_fecs_feature_override_ecc_1_sm_l1_icache_v(
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fecs_feature_override_ecc) == 1U)) {
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nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_ICACHE, true);
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}
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} else {
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if (opt_ecc_en) {
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nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_ICACHE, true);
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}
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}
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/* LTC */
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if (gr_fecs_feature_override_ecc_ltc_override_v(
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fecs_feature_override_ecc) == 1U) {
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if (gr_fecs_feature_override_ecc_ltc_v(
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fecs_feature_override_ecc) == 1U) {
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nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_LTC, true);
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}
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} else {
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if (opt_ecc_en) {
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nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_LTC, true);
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}
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}
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/* SM CBU */
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if (gr_fecs_feature_override_ecc_sm_cbu_override_v(
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fecs_feature_override_ecc) == 1U) {
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if (gr_fecs_feature_override_ecc_sm_cbu_v(
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fecs_feature_override_ecc) == 1U) {
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nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_CBU, true);
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}
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} else {
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if (opt_ecc_en) {
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nvgpu_set_enabled(g,
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NVGPU_ECC_ENABLED_SM_CBU, true);
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}
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}
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}
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}
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int gv11b_ecc_init(struct gk20a *g)
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{
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int err;
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err = NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_lrf_ecc_single_err_count);
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if (err != 0) {
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goto done;
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}
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err = NVGPU_ECC_COUNTER_INIT_PER_TPC(sm_lrf_ecc_double_err_count);
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if (err != 0) {
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goto done;
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}
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err = NVGPU_ECC_COUNTER_INIT_PER_TPC(
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sm_l1_tag_ecc_corrected_err_count);
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if (err != 0) {
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goto done;
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}
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err = NVGPU_ECC_COUNTER_INIT_PER_TPC(
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sm_l1_tag_ecc_uncorrected_err_count);
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if (err != 0) {
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goto done;
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}
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err = NVGPU_ECC_COUNTER_INIT_PER_TPC(
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sm_cbu_ecc_corrected_err_count);
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if (err != 0) {
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goto done;
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}
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err = NVGPU_ECC_COUNTER_INIT_PER_TPC(
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sm_cbu_ecc_uncorrected_err_count);
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if (err != 0) {
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goto done;
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}
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err = NVGPU_ECC_COUNTER_INIT_PER_TPC(
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sm_l1_data_ecc_corrected_err_count);
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if (err != 0) {
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goto done;
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}
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err = NVGPU_ECC_COUNTER_INIT_PER_TPC(
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sm_l1_data_ecc_uncorrected_err_count);
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if (err != 0) {
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goto done;
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}
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err = NVGPU_ECC_COUNTER_INIT_PER_TPC(
|
|
sm_icache_ecc_corrected_err_count);
|
|
if (err != 0) {
|
|
goto done;
|
|
}
|
|
err = NVGPU_ECC_COUNTER_INIT_PER_TPC(
|
|
sm_icache_ecc_uncorrected_err_count);
|
|
if (err != 0) {
|
|
goto done;
|
|
}
|
|
|
|
err = NVGPU_ECC_COUNTER_INIT_PER_GPC(
|
|
gcc_l15_ecc_corrected_err_count);
|
|
if (err != 0) {
|
|
goto done;
|
|
}
|
|
err = NVGPU_ECC_COUNTER_INIT_PER_GPC(
|
|
gcc_l15_ecc_uncorrected_err_count);
|
|
if (err != 0) {
|
|
goto done;
|
|
}
|
|
|
|
err = NVGPU_ECC_COUNTER_INIT_PER_LTS(ecc_sec_count);
|
|
if (err != 0) {
|
|
goto done;
|
|
}
|
|
err = NVGPU_ECC_COUNTER_INIT_PER_LTS(ecc_ded_count);
|
|
if (err != 0) {
|
|
goto done;
|
|
}
|
|
|
|
err = NVGPU_ECC_COUNTER_INIT_GR(fecs_ecc_uncorrected_err_count);
|
|
if (err != 0) {
|
|
goto done;
|
|
}
|
|
err = NVGPU_ECC_COUNTER_INIT_GR(fecs_ecc_corrected_err_count);
|
|
if (err != 0) {
|
|
goto done;
|
|
}
|
|
|
|
err = NVGPU_ECC_COUNTER_INIT_PER_GPC(
|
|
gpccs_ecc_uncorrected_err_count);
|
|
if (err != 0) {
|
|
goto done;
|
|
}
|
|
err = NVGPU_ECC_COUNTER_INIT_PER_GPC(
|
|
gpccs_ecc_corrected_err_count);
|
|
if (err != 0) {
|
|
goto done;
|
|
}
|
|
|
|
err = NVGPU_ECC_COUNTER_INIT_PER_GPC(
|
|
mmu_l1tlb_ecc_uncorrected_err_count);
|
|
if (err != 0) {
|
|
goto done;
|
|
}
|
|
err = NVGPU_ECC_COUNTER_INIT_PER_GPC(
|
|
mmu_l1tlb_ecc_corrected_err_count);
|
|
if (err != 0) {
|
|
goto done;
|
|
}
|
|
|
|
err = NVGPU_ECC_COUNTER_INIT_FB(mmu_l2tlb_ecc_uncorrected_err_count);
|
|
if (err != 0) {
|
|
goto done;
|
|
}
|
|
err = NVGPU_ECC_COUNTER_INIT_FB(mmu_l2tlb_ecc_corrected_err_count);
|
|
if (err != 0) {
|
|
goto done;
|
|
}
|
|
|
|
err = NVGPU_ECC_COUNTER_INIT_FB(mmu_hubtlb_ecc_uncorrected_err_count);
|
|
if (err != 0) {
|
|
goto done;
|
|
}
|
|
err = NVGPU_ECC_COUNTER_INIT_FB(mmu_hubtlb_ecc_corrected_err_count);
|
|
if (err != 0) {
|
|
goto done;
|
|
}
|
|
|
|
err = NVGPU_ECC_COUNTER_INIT_FB(
|
|
mmu_fillunit_ecc_uncorrected_err_count);
|
|
if (err != 0) {
|
|
goto done;
|
|
}
|
|
err = NVGPU_ECC_COUNTER_INIT_FB(
|
|
mmu_fillunit_ecc_corrected_err_count);
|
|
if (err != 0) {
|
|
goto done;
|
|
}
|
|
|
|
err = NVGPU_ECC_COUNTER_INIT_PMU(pmu_ecc_uncorrected_err_count);
|
|
if (err != 0) {
|
|
goto done;
|
|
}
|
|
err = NVGPU_ECC_COUNTER_INIT_PMU(pmu_ecc_corrected_err_count);
|
|
if (err != 0) {
|
|
goto done;
|
|
}
|
|
|
|
done:
|
|
if (err != 0) {
|
|
nvgpu_err(g, "ecc counter allocate failed, err=%d", err);
|
|
nvgpu_ecc_free(g);
|
|
}
|
|
|
|
return err;
|
|
}
|