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90aee0086f
renamed NVGPU_LS_PMU to NVGPU_FEATURE_LS_PMU to follow nvgpu naming standard Compile out LS PMU files when PMU RTOS support is disabled for safety build by setting NVGPU_LS_PMU build flag to 0 JIRA NVGPU-3418 Change-Id: Ib09924ac25657e932723c10be573f2f701cb7bea Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2127794 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
112 lines
3.6 KiB
C
112 lines
3.6 KiB
C
/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/pmu.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include "pmu_gk20a.h"
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#include "pmu_gp106.h"
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#include <nvgpu/hw/gp106/hw_pwr_gp106.h>
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bool gp106_pmu_is_engine_in_reset(struct gk20a *g)
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{
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u32 reg_reset;
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bool status = false;
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reg_reset = gk20a_readl(g, pwr_falcon_engine_r());
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if (reg_reset == pwr_falcon_engine_reset_true_f()) {
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status = true;
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}
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return status;
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}
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int gp106_pmu_engine_reset(struct gk20a *g, bool do_reset)
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{
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/*
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* From GP10X onwards, we are using PPWR_FALCON_ENGINE for reset. And as
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* it may come into same behavior, reading NV_PPWR_FALCON_ENGINE again
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* after Reset.
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*/
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if (do_reset) {
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gk20a_writel(g, pwr_falcon_engine_r(),
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pwr_falcon_engine_reset_false_f());
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(void) gk20a_readl(g, pwr_falcon_engine_r());
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} else {
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gk20a_writel(g, pwr_falcon_engine_r(),
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pwr_falcon_engine_reset_true_f());
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(void) gk20a_readl(g, pwr_falcon_engine_r());
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}
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return 0;
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}
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#ifdef NVGPU_FEATURE_LS_PMU
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void gp106_pmu_setup_apertures(struct gk20a *g)
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{
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struct mm_gk20a *mm = &g->mm;
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u32 inst_block_ptr;
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/* PMU TRANSCFG */
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/* setup apertures - virtual */
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gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
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pwr_fbif_transcfg_mem_type_physical_f() |
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pwr_fbif_transcfg_target_local_fb_f());
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gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
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pwr_fbif_transcfg_mem_type_virtual_f());
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/* setup apertures - physical */
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gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
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pwr_fbif_transcfg_mem_type_physical_f() |
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pwr_fbif_transcfg_target_local_fb_f());
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gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
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pwr_fbif_transcfg_mem_type_physical_f() |
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pwr_fbif_transcfg_target_coherent_sysmem_f());
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gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
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pwr_fbif_transcfg_mem_type_physical_f() |
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pwr_fbif_transcfg_target_noncoherent_sysmem_f());
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/* PMU Config */
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gk20a_writel(g, pwr_falcon_itfen_r(),
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gk20a_readl(g, pwr_falcon_itfen_r()) |
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pwr_falcon_itfen_ctxen_enable_f());
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inst_block_ptr = nvgpu_inst_block_ptr(g, &mm->pmu.inst_block);
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gk20a_writel(g, pwr_pmu_new_instblk_r(),
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pwr_pmu_new_instblk_ptr_f(inst_block_ptr) |
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pwr_pmu_new_instblk_valid_f(1) |
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nvgpu_aperture_mask(g, &mm->pmu.inst_block,
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pwr_pmu_new_instblk_target_sys_ncoh_f(),
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pwr_pmu_new_instblk_target_sys_coh_f(),
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pwr_pmu_new_instblk_target_fb_f()));
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}
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u32 gp106_pmu_falcon_base_addr(void)
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{
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return pwr_falcon_irqsset_r();
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}
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bool gp106_is_pmu_supported(struct gk20a *g)
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{
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return true;
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}
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#endif
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