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05ed37ae3a
This patch does the following:
(1) Removes the usage of hw headers in SDL unit. For this purpose, it moves
the initialization required for errors that can be injected using hw
support, error injection function. Further, it passes the required
information to SDL via hal layers.
(2) Renames (i) PWR as PMU, (ii) nvgpu_report_ecc_parity_err to
nvgpu_report_ecc_err.
Jira NVGPU-3235
Change-Id: I69290af78c09fbb5b792058e7bc6cc8b6ba340c9
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112837
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
54 lines
2.3 KiB
C
54 lines
2.3 KiB
C
/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef PMU_GV11B_H
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#define PMU_GV11B_H
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#include <nvgpu/nvgpu_err.h>
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#include <nvgpu/types.h>
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struct gk20a;
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struct nvgpu_hw_err_inject_info;
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struct nvgpu_hw_err_inject_info_desc;
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bool gv11b_pmu_is_debug_mode_en(struct gk20a *g);
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void gv11b_pmu_flcn_setup_boot_config(struct gk20a *g);
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void gv11b_setup_apertures(struct gk20a *g);
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void gv11b_write_dmatrfbase(struct gk20a *g, u32 addr);
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u32 gv11b_pmu_falcon_base_addr(void);
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void gv11b_secured_pmu_start(struct gk20a *g);
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bool gv11b_is_pmu_supported(struct gk20a *g);
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int gv11b_pmu_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu,
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u32 args_offset);
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void gv11b_pmu_setup_elpg(struct gk20a *g);
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u32 gv11b_pmu_get_irqdest(struct gk20a *g);
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void gv11b_pmu_handle_ext_irq(struct gk20a *g, u32 intr0);
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void gv11b_clear_pmu_bar0_host_err_status(struct gk20a *g);
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int gv11b_pmu_bar0_error_status(struct gk20a *g, u32 *bar0_status,
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u32 *etype);
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bool gv11b_pmu_validate_mem_integrity(struct gk20a *g);
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struct nvgpu_hw_err_inject_info_desc * gv11b_pmu_intr_get_err_desc(struct gk20a *g);
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int gv11b_pmu_inject_ecc_error(struct gk20a *g,
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struct nvgpu_hw_err_inject_info *err, u32 error_info);
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#endif /* PMU_GV11B_H */
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