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The ctxsw ucode saves all the ctxsw'ed TPC priv registers in the TPC priv segment of the ctxsw image. In ga10b, these registers can be stored in either of the two arrangements: - INTERLEAVED: means the format is sorted by address first, then by TPC number - MIGRATION: exact opposite of interleaved. Update HAL functions gr_ga10b_process_context_buffer_priv_segment, gr_ga10b_find_priv_offset_in_buffer to detect the register layout and calculate the register offset accordingly. Bug 200737000 Bug 3532165 Change-Id: I305509cf89498cb0c2c5bfa1d867272bdf5f42b3 Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2665491 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>