mirror of
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b386768d32
The message to tell RM server to unbind channel has to be sent after client unbinds the channel and before client calls tsg release. The channel has to belong to a tsg on RM server before client submit a runlist to remove the channel. Or there's a bare channel problem. By moving .tsg_unbind_channl one layer lower, gk20a_tsg_unbind_channel() will be common functions for all chip, and it'll call tsg release after call .tsg_unbind_channel. So vgpu won't need to worry about tsg was released before sending msg to RM server. Bug 200382695 Bug 200382785 Change-Id: I32acc122f3f9d5d0628049ccf673225f9e90c87a Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1645383 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
157 lines
3.8 KiB
C
157 lines
3.8 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/tegra_vgpu.h>
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#include "gk20a/gk20a.h"
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#include "gk20a/channel_gk20a.h"
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#include "gk20a/tsg_gk20a.h"
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#include "common/linux/platform_gk20a.h"
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#include "vgpu.h"
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#include "fifo_vgpu.h"
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#include <nvgpu/bug.h>
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int vgpu_tsg_open(struct tsg_gk20a *tsg)
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{
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struct tegra_vgpu_cmd_msg msg = {};
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struct tegra_vgpu_tsg_open_rel_params *p =
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&msg.params.tsg_open;
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int err;
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gk20a_dbg_fn("");
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msg.cmd = TEGRA_VGPU_CMD_TSG_OPEN;
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msg.handle = vgpu_get_handle(tsg->g);
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p->tsg_id = tsg->tsgid;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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if (err) {
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nvgpu_err(tsg->g,
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"vgpu_tsg_open failed, tsgid %d", tsg->tsgid);
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}
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return err;
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}
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void vgpu_tsg_release(struct tsg_gk20a *tsg)
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{
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struct tegra_vgpu_cmd_msg msg = {};
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struct tegra_vgpu_tsg_open_rel_params *p =
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&msg.params.tsg_release;
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int err;
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gk20a_dbg_fn("");
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msg.cmd = TEGRA_VGPU_CMD_TSG_RELEASE;
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msg.handle = vgpu_get_handle(tsg->g);
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p->tsg_id = tsg->tsgid;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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if (err) {
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nvgpu_err(tsg->g,
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"vgpu_tsg_release failed, tsgid %d", tsg->tsgid);
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}
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}
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int vgpu_enable_tsg(struct tsg_gk20a *tsg)
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{
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struct gk20a *g = tsg->g;
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struct channel_gk20a *ch;
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nvgpu_rwsem_down_read(&tsg->ch_list_lock);
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nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry)
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g->ops.fifo.enable_channel(ch);
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nvgpu_rwsem_up_read(&tsg->ch_list_lock);
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return 0;
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}
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int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg,
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struct channel_gk20a *ch)
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{
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struct tegra_vgpu_cmd_msg msg = {};
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struct tegra_vgpu_tsg_bind_unbind_channel_params *p =
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&msg.params.tsg_bind_unbind_channel;
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int err;
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gk20a_dbg_fn("");
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err = gk20a_tsg_bind_channel(tsg, ch);
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if (err)
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return err;
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msg.cmd = TEGRA_VGPU_CMD_TSG_BIND_CHANNEL;
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msg.handle = vgpu_get_handle(tsg->g);
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p->tsg_id = tsg->tsgid;
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p->ch_handle = ch->virt_ctx;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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if (err) {
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nvgpu_err(tsg->g,
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"vgpu_tsg_bind_channel failed, ch %d tsgid %d",
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ch->chid, tsg->tsgid);
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gk20a_tsg_unbind_channel(ch);
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}
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return err;
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}
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int vgpu_tsg_unbind_channel(struct channel_gk20a *ch)
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{
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struct tegra_vgpu_cmd_msg msg = {};
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struct tegra_vgpu_tsg_bind_unbind_channel_params *p =
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&msg.params.tsg_bind_unbind_channel;
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int err;
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gk20a_dbg_fn("");
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err = gk20a_fifo_tsg_unbind_channel(ch);
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if (err)
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return err;
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msg.cmd = TEGRA_VGPU_CMD_TSG_UNBIND_CHANNEL;
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msg.handle = vgpu_get_handle(ch->g);
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p->ch_handle = ch->virt_ctx;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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WARN_ON(err);
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return err;
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}
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int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice)
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{
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struct tegra_vgpu_cmd_msg msg = {0};
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struct tegra_vgpu_tsg_timeslice_params *p =
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&msg.params.tsg_timeslice;
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int err;
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gk20a_dbg_fn("");
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msg.cmd = TEGRA_VGPU_CMD_TSG_SET_TIMESLICE;
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msg.handle = vgpu_get_handle(tsg->g);
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p->tsg_id = tsg->tsgid;
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p->timeslice_us = timeslice;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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WARN_ON(err);
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if (!err)
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tsg->timeslice_us = timeslice;
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return err;
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}
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