mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 01:50:07 +03:00
cd4b2f642c
Refactor read accesses to the ccsr_channel register for channel state to be done via a channel HAL op for all chips. A new op called read_state is added for this; information needed by other units is collected in a new struct nvgpu_channel_hw_state. Jira NVGPU-1307 Change-Id: Iff9385c08e17ac086d97f5771a54b56b2727e3c4 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2017266 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
37 lines
1.6 KiB
C
37 lines
1.6 KiB
C
/*
|
|
* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be included in
|
|
* all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
|
* DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
#ifndef FIFO_CHANNEL_GK20A_H
|
|
#define FIFO_CHANNEL_GK20A_H
|
|
|
|
struct channel_gk20a;
|
|
struct gk20a;
|
|
struct nvgpu_channel_hw_state;
|
|
|
|
void gk20a_channel_enable(struct channel_gk20a *ch);
|
|
void gk20a_channel_disable(struct channel_gk20a *ch);
|
|
void gk20a_channel_unbind(struct channel_gk20a *ch);
|
|
void gk20a_channel_read_state(struct gk20a *g, struct channel_gk20a *ch,
|
|
struct nvgpu_channel_hw_state *state);
|
|
|
|
#endif /* FIFO_CHANNEL_GK20A_H */
|