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c02bccd6db
The type for the timeout parameter to the NVGPU_COND_WAIT and NVGPU_COND_WAIT_INTERRUPTIBLE macros was too weak. This updates these macros to require a u32 for the timeout. Users of the macros are updated to be compliant as necessary. This addresses MISRA 10.3 violations for implicit conversions of types of different size or essential type. JIRA NVGPU-1008 Change-Id: I12368dfa81b137c35bd056668c1867f03a73b7aa Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2017503 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
93 lines
2.7 KiB
C
93 lines
2.7 KiB
C
/*
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* GK20A Master Control
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*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/io.h>
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#include <nvgpu/mc.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/hw/gm20b/hw_mc_gm20b.h>
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u32 nvgpu_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev)
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{
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u32 val = __nvgpu_readl(g, mc_boot_0_r());
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if (val != 0xffffffffU) {
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if (arch != NULL) {
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*arch = mc_boot_0_architecture_v(val) <<
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NVGPU_GPU_ARCHITECTURE_SHIFT;
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}
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if (impl != NULL) {
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*impl = mc_boot_0_implementation_v(val);
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}
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if (rev != NULL) {
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*rev = (mc_boot_0_major_revision_v(val) << 4) |
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mc_boot_0_minor_revision_v(val);
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}
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}
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return val;
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}
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/**
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* cyclic_delta - Returns delta of cyclic integers a and b.
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*
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* @a - First integer
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* @b - Second integer
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*
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* Note: if a is ahead of b, delta is positive.
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*/
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static int cyclic_delta(int a, int b)
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{
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return a - b;
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}
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/**
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* nvgpu_wait_for_deferred_interrupts - Wait for interrupts to complete
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*
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* @g - The GPU to wait on.
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*
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* Waits until all interrupt handlers that have been scheduled to run have
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* completed.
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*/
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void nvgpu_wait_for_deferred_interrupts(struct gk20a *g)
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{
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int stall_irq_threshold = nvgpu_atomic_read(&g->hw_irq_stall_count);
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int nonstall_irq_threshold = nvgpu_atomic_read(&g->hw_irq_nonstall_count);
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/* wait until all stalling irqs are handled */
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NVGPU_COND_WAIT(&g->sw_irq_stall_last_handled_cond,
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cyclic_delta(stall_irq_threshold,
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nvgpu_atomic_read(&g->sw_irq_stall_last_handled))
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<= 0, 0U);
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/* wait until all non-stalling irqs are handled */
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NVGPU_COND_WAIT(&g->sw_irq_nonstall_last_handled_cond,
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cyclic_delta(nonstall_irq_threshold,
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nvgpu_atomic_read(&g->sw_irq_nonstall_last_handled))
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<= 0, 0U);
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}
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