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303fc7496c
MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals or casting operands to have same type of operands when an arithmetic operation is performed. This fixes violations where an arithmetic operation is performed on signed and unsigned int types. JIRA NVGPU-992 Change-Id: I27e3e59c3559c377b4bd3cbcfced90fdf90350f2 Signed-off-by: Sai Nikhil <snikhil@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1921459 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
67 lines
2.8 KiB
C
67 lines
2.8 KiB
C
/*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_MC_TU104_H
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#define NVGPU_MC_TU104_H
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#include <nvgpu/types.h>
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#define NV_CPU_INTR_SUBTREE_TO_TOP_IDX(i) ((i) / 32U)
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#define NV_CPU_INTR_SUBTREE_TO_TOP_BIT(i) ((i) % 32U)
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#define NV_CPU_INTR_SUBTREE_TO_LEAF_REG0(i) ((i)*2U)
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#define NV_CPU_INTR_SUBTREE_TO_LEAF_REG1(i) (((i)*2U) + 1U)
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#define NV_CPU_INTR_GPU_VECTOR_TO_LEAF_REG(i) ((i) / 32U)
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#define NV_CPU_INTR_GPU_VECTOR_TO_LEAF_BIT(i) ((i) % 32U)
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#define NV_CPU_INTR_GPU_VECTOR_TO_SUBTREE(i) ((NV_CPU_INTR_GPU_VECTOR_TO_LEAF_REG(i)) / 2U)
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#define NV_CPU_INTR_TOP_NONSTALL_SUBTREE 0U
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struct gk20a;
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void intr_tu104_leaf_en_set(struct gk20a *g, u32 leaf_reg_index,
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u32 leaf_reg_bit);
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void intr_tu104_leaf_en_clear(struct gk20a *g, u32 leaf_reg_index,
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u32 leaf_reg_bit);
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void intr_tu104_top_en_set(struct gk20a *g, u32 top_reg_index,
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u32 top_reg_bit);
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void intr_tu104_vector_en_set(struct gk20a *g, u32 intr_vector);
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void intr_tu104_vector_en_clear(struct gk20a *g, u32 intr_vector);
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bool intr_tu104_vector_intr_pending(struct gk20a *g, u32 intr_vector);
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void intr_tu104_intr_clear_leaf_vector(struct gk20a *g, u32 intr_vector);
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void intr_tu104_mask(struct gk20a *g);
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void intr_tu104_enable(struct gk20a *g);
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u32 intr_tu104_stall(struct gk20a *g);
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void intr_tu104_stall_pause(struct gk20a *g);
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void intr_tu104_stall_resume(struct gk20a *g);
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u32 intr_tu104_nonstall(struct gk20a *g);
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void intr_tu104_nonstall_pause(struct gk20a *g);
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void intr_tu104_nonstall_resume(struct gk20a *g);
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u32 intr_tu104_isr_nonstall(struct gk20a *g);
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bool intr_tu104_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0);
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void intr_tu104_log_pending_intrs(struct gk20a *g);
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void mc_tu104_fbpa_isr(struct gk20a *g);
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void mc_tu104_ltc_isr(struct gk20a *g);
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#endif /* NVGPU_MC_TU104_H */
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