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e7987729bd
MISRA Rule 10.3 does not allow value of expression to be assigned to an object with a narrower essential type or to a different essential type category. Fix such 10.3 violations in nvlink code by type-casting (when sure there will be no overflows) or by changing the data-type of variables JIRA NVGPU-1921 Change-Id: Iab103a7f0c23cf2a047152cbd76c0b55b3cc947c Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2012811 Reviewed-by: Philip Elcan <pelcan@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
60 lines
2.8 KiB
C
60 lines
2.8 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_NVLINK_GV100_H
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#define NVGPU_NVLINK_GV100_H
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#define GV100_CONNECTED_LINK_MASK 0x8
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struct gk20a;
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int gv100_nvlink_discover_ioctrl(struct gk20a *g);
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int gv100_nvlink_discover_link(struct gk20a *g);
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int gv100_nvlink_init(struct gk20a *g);
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int gv100_nvlink_minion_send_command(struct gk20a *g, u32 link_id, u32 command,
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u32 scratch_0, bool sync);
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int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask);
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int gv100_nvlink_minion_data_ready_en(struct gk20a *g,
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unsigned long link_mask, bool sync);
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void gv100_nvlink_get_connected_link_mask(u32 *link_mask);
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void gv100_nvlink_set_sw_war(struct gk20a *g, u32 link_id);
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/* API */
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int gv100_nvlink_link_early_init(struct gk20a *g, unsigned long mask);
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enum nvgpu_nvlink_link_mode gv100_nvlink_link_get_mode(struct gk20a *g,
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u32 link_id);
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u32 gv100_nvlink_link_get_state(struct gk20a *g, u32 link_id);
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int gv100_nvlink_link_set_mode(struct gk20a *g, u32 link_id,
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enum nvgpu_nvlink_link_mode mode);
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enum nvgpu_nvlink_sublink_mode gv100_nvlink_link_get_sublink_mode(
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struct gk20a *g, u32 link_id, bool is_rx_sublink);
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u32 gv100_nvlink_link_get_tx_sublink_state(struct gk20a *g, u32 link_id);
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u32 gv100_nvlink_link_get_rx_sublink_state(struct gk20a *g, u32 link_id);
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int gv100_nvlink_link_set_sublink_mode(struct gk20a *g, u32 link_id,
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bool is_rx_sublink, enum nvgpu_nvlink_sublink_mode mode);
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int gv100_nvlink_interface_init(struct gk20a *g);
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int gv100_nvlink_interface_disable(struct gk20a *g);
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int gv100_nvlink_shutdown(struct gk20a *g);
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int gv100_nvlink_early_init(struct gk20a *g);
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int gv100_nvlink_speed_config(struct gk20a *g);
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u32 gv100_nvlink_falcon_base_addr(struct gk20a *g);
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#endif
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