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b140620f1d
Add a macro for invalid CE ctx id. This makes the code more readable and the macro fixes a few MISRA rule 10.1 violations. JIRA NVGPU-1006 Change-Id: I0979dd692d9524f3a5e03bf225b4dba0fe167710 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1982992 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
154 lines
4.5 KiB
C
154 lines
4.5 KiB
C
/*
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* drivers/video/tegra/host/gk20a/fifo_gk20a.h
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*
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* GK20A graphics copy engine (gr host)
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*
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* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GK20A_CE2_GK20A_H
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#define NVGPU_GK20A_CE2_GK20A_H
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struct channel_gk20a;
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struct tsg_gk20a;
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struct gk20a;
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void gk20a_ce2_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
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u32 gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
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#define NVGPU_CE_INVAL_CTX_ID ~U32(0U)
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/* CE command utility macros */
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#define NVGPU_CE_LOWER_ADDRESS_OFFSET_MASK 0xffffffffU
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#define NVGPU_CE_UPPER_ADDRESS_OFFSET_MASK 0xffU
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#define NVGPU_CE_MAX_INFLIGHT_JOBS 32U
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#define NVGPU_CE_MAX_COMMAND_BUFF_BYTES_PER_KICKOFF 256U
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/* dma launch_flags */
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/* location */
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#define NVGPU_CE_SRC_LOCATION_COHERENT_SYSMEM BIT32(0)
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#define NVGPU_CE_SRC_LOCATION_NONCOHERENT_SYSMEM BIT32(1)
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#define NVGPU_CE_SRC_LOCATION_LOCAL_FB BIT32(2)
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#define NVGPU_CE_DST_LOCATION_COHERENT_SYSMEM BIT32(3)
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#define NVGPU_CE_DST_LOCATION_NONCOHERENT_SYSMEM BIT32(4)
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#define NVGPU_CE_DST_LOCATION_LOCAL_FB BIT32(5)
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/* memory layout */
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#define NVGPU_CE_SRC_MEMORY_LAYOUT_PITCH BIT32(6)
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#define NVGPU_CE_SRC_MEMORY_LAYOUT_BLOCKLINEAR BIT32(7)
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#define NVGPU_CE_DST_MEMORY_LAYOUT_PITCH BIT32(8)
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#define NVGPU_CE_DST_MEMORY_LAYOUT_BLOCKLINEAR BIT32(9)
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/* transfer type */
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#define NVGPU_CE_DATA_TRANSFER_TYPE_PIPELINED BIT32(10)
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#define NVGPU_CE_DATA_TRANSFER_TYPE_NON_PIPELINED BIT32(11)
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/* CE operation mode */
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#define NVGPU_CE_PHYS_MODE_TRANSFER BIT32(0)
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#define NVGPU_CE_MEMSET BIT32(1)
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/* CE app state machine flags */
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enum {
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NVGPU_CE_ACTIVE = (1 << 0),
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NVGPU_CE_SUSPEND = (1 << 1),
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};
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/* gpu context state machine flags */
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enum {
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NVGPU_CE_GPU_CTX_ALLOCATED = (1 << 0),
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NVGPU_CE_GPU_CTX_DELETED = (1 << 1),
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};
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/* global ce app db */
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struct gk20a_ce_app {
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bool initialised;
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struct nvgpu_mutex app_mutex;
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int app_state;
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struct nvgpu_list_node allocated_contexts;
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u32 ctx_count;
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u32 next_ctx_id;
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};
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/* ce context db */
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struct gk20a_gpu_ctx {
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struct gk20a *g;
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u32 ctx_id;
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struct nvgpu_mutex gpu_ctx_mutex;
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int gpu_ctx_state;
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/* tsg related data */
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struct tsg_gk20a *tsg;
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/* channel related data */
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struct channel_gk20a *ch;
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struct vm_gk20a *vm;
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/* cmd buf mem_desc */
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struct nvgpu_mem cmd_buf_mem;
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struct gk20a_fence *postfences[NVGPU_CE_MAX_INFLIGHT_JOBS];
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struct nvgpu_list_node list;
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u32 cmd_buf_read_queue_offset;
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};
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static inline struct gk20a_gpu_ctx *
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gk20a_gpu_ctx_from_list(struct nvgpu_list_node *node)
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{
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return (struct gk20a_gpu_ctx *)
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((uintptr_t)node - offsetof(struct gk20a_gpu_ctx, list));
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};
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/* global CE app related apis */
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int gk20a_init_ce_support(struct gk20a *g);
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void gk20a_ce_suspend(struct gk20a *g);
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void gk20a_ce_destroy(struct gk20a *g);
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/* CE app utility functions */
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u32 gk20a_ce_create_context(struct gk20a *g,
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int runlist_id,
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int timeslice,
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int runlist_level);
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int gk20a_ce_execute_ops(struct gk20a *g,
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u32 ce_ctx_id,
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u64 src_buf,
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u64 dst_buf,
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u64 size,
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unsigned int payload,
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u32 launch_flags,
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u32 request_operation,
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u32 submit_flags,
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struct gk20a_fence **gk20a_fence_out);
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void gk20a_ce_delete_context_priv(struct gk20a *g,
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u32 ce_ctx_id);
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void gk20a_ce_delete_context(struct gk20a *g,
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u32 ce_ctx_id);
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int gk20a_ce_prepare_submit(u64 src_buf,
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u64 dst_buf,
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u64 size,
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u32 *cmd_buf_cpu_va,
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u32 max_cmd_buf_size,
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unsigned int payload,
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u32 launch_flags,
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u32 request_operation,
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u32 dma_copy_class);
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#endif /*NVGPU_GK20A_CE2_GK20A_H*/
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