mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-25 11:04:51 +03:00
b117f40f6c
tegra_fuse_readl is supported in upstream. Separate out the functions using this API from the config CONFIG_NVGPU_TEGRA_FUSE. Following four fuses are defined in downstream kernel repositories in tegra fuse header. It can be incorporated in upstream if nvgpu starts reading those fuses using nvmem APIs. Hence define those fuse offsets in nvgpu itself for now. 1. FUSE_RESERVED_CALIB0_0 2. FUSE_GCPLEX_CONFIG_FUSE_0 3. FUSE_PDI0 4. FUSE_PDI1 Bug 200625647 Change-Id: I8da8c0c3a0682fdab806fa57035fedd29ef22c26 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2369955 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com> Reviewed-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
143 lines
3.9 KiB
C
143 lines
3.9 KiB
C
/*
|
|
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be included in
|
|
* all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
|
* DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
#ifndef NVGPU_FUSE_H
|
|
#define NVGPU_FUSE_H
|
|
/**
|
|
* @file
|
|
*
|
|
* Interface for fuse ops.
|
|
*/
|
|
|
|
struct gk20a;
|
|
|
|
#include <nvgpu/types.h>
|
|
#include <nvgpu/errno.h>
|
|
|
|
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
|
|
#include "include/nvgpu/nvgpu_next_fuse.h"
|
|
#endif
|
|
|
|
#ifdef CONFIG_NVGPU_NON_FUSA
|
|
int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g, int *id);
|
|
int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val);
|
|
#endif /* CONFIG_NVGPU_NON_FUSA */
|
|
|
|
/**
|
|
* @brief - Reads GCPLEX_CONFIG_FUSE configuration.
|
|
*
|
|
* @param g [in] - GPU super structure.
|
|
* @param val [out] - Populated with register GCPLEX_CONFIG_FUSE value.
|
|
*
|
|
* - Provide information about the GPU complex configuration.
|
|
*
|
|
* @return 0 on success.
|
|
*
|
|
*/
|
|
int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val);
|
|
|
|
/**
|
|
* @brief - Reads the per-device identifier fuses.
|
|
*
|
|
* @param g [in] - GPU super structure.
|
|
* @param pdi [out] - Per-device identifier
|
|
*
|
|
* The per-device identifier fuses are FUSE_PDI0 and FUSE_PDI1.
|
|
*
|
|
* @return 0 on success
|
|
*/
|
|
int nvgpu_tegra_fuse_read_per_device_identifier(struct gk20a *g, u64 *pdi);
|
|
|
|
#ifdef CONFIG_NVGPU_TEGRA_FUSE
|
|
|
|
/**
|
|
* @brief - Write Fuse bypass register which controls fuse bypass.
|
|
*
|
|
* @param g [in] - GPU super structure.
|
|
* @param val [in]- 0 : DISABLED, 1 : ENABLED
|
|
*
|
|
* - Write 0/1 to control the fuse bypass.
|
|
*
|
|
* @return none.
|
|
*/
|
|
void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val);
|
|
|
|
/**
|
|
* @brief - Enable software write access
|
|
*
|
|
* @param g [in] - GPU super structure.
|
|
* @param val [in] - 0 : READWRITE, 1 : READONLY
|
|
*
|
|
* - Bit 0 of the register is the write control register. When set to 1,
|
|
* it disables writes to chip.
|
|
*
|
|
* @return none.
|
|
*/
|
|
void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val);
|
|
|
|
/**
|
|
* @brief - Disable TPC0
|
|
*
|
|
* @param g [in] - GPU super structure.
|
|
* @param val [in] - 1 : DISABLED, 0 : ENABLED
|
|
*
|
|
* - Write 1/0 to fuse tpc disable register to disable/enable the TPC0.
|
|
*
|
|
* @return none.
|
|
*/
|
|
void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g, u32 val);
|
|
|
|
/**
|
|
* @brief - Disable TPC1
|
|
*
|
|
* @param g [in] - GPU super structure.
|
|
* @param val [in] - 1 : DISABLED, 0 : ENABLED
|
|
*
|
|
* - Write 1/0 to fuse tpc disable register to disable/enable the TPC1.
|
|
*
|
|
* @return none.
|
|
*/
|
|
void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val);
|
|
|
|
#else /* CONFIG_NVGPU_TEGRA_FUSE */
|
|
|
|
static inline void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val)
|
|
{
|
|
}
|
|
|
|
static inline void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val)
|
|
{
|
|
}
|
|
|
|
static inline void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g,
|
|
u32 val)
|
|
{
|
|
}
|
|
|
|
static inline void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g,
|
|
u32 val)
|
|
{
|
|
}
|
|
|
|
#endif /* CONFIG_NVGPU_TEGRA_FUSE */
|
|
|
|
#endif /* NVGPU_FUSE_H */
|