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MISRA rule 14.4 doesn't allow the usage of integer types as booleans in the controlling expression of an if statement or an iteration statement Fix violations where the integer variables err, ret, status are used as booleans in the controlling expression of if and loop statements. JIRA NVGPU-1019 Change-Id: Ia950828797b8eff4bc754269ea2d9fa272f59436 Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1919111 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Scott Long <scottl@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
233 lines
5.9 KiB
C
233 lines
5.9 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/atomic.h>
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#include <nvgpu/allocator.h>
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#include <nvgpu/kmem.h>
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#include <nvgpu/barrier.h>
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#include "lockless_allocator_priv.h"
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static u64 nvgpu_lockless_alloc_length(struct nvgpu_allocator *a)
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{
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struct nvgpu_lockless_allocator *pa = a->priv;
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return pa->length;
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}
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static u64 nvgpu_lockless_alloc_base(struct nvgpu_allocator *a)
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{
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struct nvgpu_lockless_allocator *pa = a->priv;
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return pa->base;
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}
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static bool nvgpu_lockless_alloc_inited(struct nvgpu_allocator *a)
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{
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struct nvgpu_lockless_allocator *pa = a->priv;
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bool inited = pa->inited;
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nvgpu_smp_rmb();
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return inited;
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}
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static u64 nvgpu_lockless_alloc_end(struct nvgpu_allocator *a)
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{
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struct nvgpu_lockless_allocator *pa = a->priv;
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return pa->base + pa->length;
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}
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static u64 nvgpu_lockless_alloc(struct nvgpu_allocator *a, u64 len)
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{
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struct nvgpu_lockless_allocator *pa = a->priv;
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int head, new_head, ret;
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u64 addr = 0;
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if (len != pa->blk_size) {
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return 0;
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}
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head = NV_ACCESS_ONCE(pa->head);
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while (head >= 0) {
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new_head = NV_ACCESS_ONCE(pa->next[head]);
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ret = cmpxchg(&pa->head, head, new_head);
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if (ret == head) {
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addr = pa->base + head * pa->blk_size;
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nvgpu_atomic_inc(&pa->nr_allocs);
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alloc_dbg(a, "Alloc node # %d @ addr 0x%llx", head,
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addr);
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break;
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}
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head = NV_ACCESS_ONCE(pa->head);
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}
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if (addr) {
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alloc_dbg(a, "Alloc node # %d @ addr 0x%llx", head, addr);
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} else {
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alloc_dbg(a, "Alloc failed!");
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}
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return addr;
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}
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static void nvgpu_lockless_free(struct nvgpu_allocator *a, u64 addr)
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{
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struct nvgpu_lockless_allocator *pa = a->priv;
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int head, ret;
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u64 cur_idx;
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cur_idx = (addr - pa->base) / pa->blk_size;
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alloc_dbg(a, "Free node # %llu @ addr 0x%llx", cur_idx, addr);
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while (1) {
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head = NV_ACCESS_ONCE(pa->head);
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NV_ACCESS_ONCE(pa->next[cur_idx]) = head;
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ret = cmpxchg(&pa->head, head, cur_idx);
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if (ret == head) {
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nvgpu_atomic_dec(&pa->nr_allocs);
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alloc_dbg(a, "Free node # %llu", cur_idx);
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break;
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}
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}
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}
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static void nvgpu_lockless_alloc_destroy(struct nvgpu_allocator *a)
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{
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struct nvgpu_lockless_allocator *pa = a->priv;
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#ifdef CONFIG_DEBUG_FS
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nvgpu_fini_alloc_debug(a);
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#endif
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nvgpu_vfree(a->g, pa->next);
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nvgpu_kfree(nvgpu_alloc_to_gpu(a), pa);
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}
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#ifdef __KERNEL__
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static void nvgpu_lockless_print_stats(struct nvgpu_allocator *a,
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struct seq_file *s, int lock)
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{
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struct nvgpu_lockless_allocator *pa = a->priv;
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__alloc_pstat(s, a, "Lockless allocator params:");
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__alloc_pstat(s, a, " start = 0x%llx", pa->base);
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__alloc_pstat(s, a, " end = 0x%llx", pa->base + pa->length);
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/* Actual stats. */
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__alloc_pstat(s, a, "Stats:");
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__alloc_pstat(s, a, " Number allocs = %d",
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nvgpu_atomic_read(&pa->nr_allocs));
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__alloc_pstat(s, a, " Number free = %d",
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pa->nr_nodes - nvgpu_atomic_read(&pa->nr_allocs));
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}
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#endif
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static const struct nvgpu_allocator_ops pool_ops = {
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.alloc = nvgpu_lockless_alloc,
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.free = nvgpu_lockless_free,
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.base = nvgpu_lockless_alloc_base,
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.length = nvgpu_lockless_alloc_length,
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.end = nvgpu_lockless_alloc_end,
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.inited = nvgpu_lockless_alloc_inited,
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.fini = nvgpu_lockless_alloc_destroy,
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#ifdef __KERNEL__
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.print_stats = nvgpu_lockless_print_stats,
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#endif
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};
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int nvgpu_lockless_allocator_init(struct gk20a *g, struct nvgpu_allocator *na,
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const char *name, u64 base, u64 length,
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u64 blk_size, u64 flags)
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{
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int i;
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int err;
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int nr_nodes;
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u64 count;
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struct nvgpu_lockless_allocator *a;
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if (blk_size == 0ULL) {
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return -EINVAL;
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}
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/*
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* Ensure we have space for at least one node & there's no overflow.
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* In order to control memory footprint, we require count < INT_MAX
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*/
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count = length / blk_size;
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if (base == 0ULL || count == 0ULL || count > INT_MAX) {
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return -EINVAL;
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}
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a = nvgpu_kzalloc(g, sizeof(struct nvgpu_lockless_allocator));
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if (a == NULL) {
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return -ENOMEM;
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}
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err = nvgpu_alloc_common_init(na, g, name, a, false, &pool_ops);
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if (err != 0) {
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goto fail;
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}
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a->next = nvgpu_vzalloc(g, sizeof(*a->next) * count);
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if (a->next == NULL) {
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err = -ENOMEM;
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goto fail;
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}
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/* chain the elements together to form the initial free list */
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nr_nodes = (int)count;
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for (i = 0; i < nr_nodes; i++) {
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a->next[i] = i + 1;
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}
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a->next[nr_nodes - 1] = -1;
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a->base = base;
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a->length = length;
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a->blk_size = blk_size;
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a->nr_nodes = nr_nodes;
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a->flags = flags;
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nvgpu_atomic_set(&a->nr_allocs, 0);
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nvgpu_smp_wmb();
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a->inited = true;
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#ifdef CONFIG_DEBUG_FS
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nvgpu_init_alloc_debug(g, na);
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#endif
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alloc_dbg(na, "New allocator: type lockless");
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alloc_dbg(na, " base 0x%llx", a->base);
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alloc_dbg(na, " nodes %d", a->nr_nodes);
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alloc_dbg(na, " blk_size 0x%llx", a->blk_size);
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alloc_dbg(na, " flags 0x%llx", a->flags);
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return 0;
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fail:
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nvgpu_kfree(g, a);
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return err;
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}
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