mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 18:16:01 +03:00
e5824d8014
- update gp106 pg engine init/list/features HALs to support MS engine - Added defines & interface for lpwr tables read from vbios. - lpwr module which reads idx/gr/ms table from vbios to map rppg/mscg support with respective p-state - lpwr module public functions to control lpwr features enable/disable mscg/rppg & mclk-change request whenever change in mclk-change parameters - lpwr public functions to know rppg/mscg support for requested pstate, - added mutex t prevent PG transition while arbiter executes pstate transition - nvgpu_clk_arb_get_current_pstate() of clk arbiter to get current pstate JIRA DNVGPU-71 Change-Id: Ifcd640cc19ef630be1e2a9ba07ec84023d8202a0 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247553 (cherry picked from commit 8a441dea2410e1b5196ef24e56a7768b6980e46b) Reviewed-on: http://git-master/r/1270989 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
72 lines
2.2 KiB
C
72 lines
2.2 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include "gk20a/gk20a.h"
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#ifndef _CLK_ARB_H_
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#define _CLK_ARB_H_
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struct nvgpu_clk_arb;
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struct nvgpu_clk_session;
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int nvgpu_clk_arb_init_arbiter(struct gk20a *g);
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int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
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u16 *min_mhz, u16 *max_mhz);
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int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g,
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u32 api_domain, u16 *actual_mhz);
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int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g,
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u32 api_domain, u16 *effective_mhz);
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int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g,
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u32 api_domain, u32 *max_points, u16 *fpoints);
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u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g);
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void nvgpu_clk_arb_cleanup_arbiter(struct gk20a *g);
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int nvgpu_clk_arb_install_session_fd(struct gk20a *g,
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struct nvgpu_clk_session *session);
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int nvgpu_clk_arb_init_session(struct gk20a *g,
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struct nvgpu_clk_session **_session);
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void nvgpu_clk_arb_release_session(struct gk20a *g,
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struct nvgpu_clk_session *session);
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int nvgpu_clk_arb_commit_request_fd(struct gk20a *g,
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struct nvgpu_clk_session *session, int request_fd);
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int nvgpu_clk_arb_set_session_target_mhz(struct nvgpu_clk_session *session,
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int fd, u32 api_domain, u16 target_mhz);
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int nvgpu_clk_arb_get_session_target_mhz(struct nvgpu_clk_session *session,
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u32 api_domain, u16 *target_mhz);
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int nvgpu_clk_arb_install_event_fd(struct gk20a *g,
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struct nvgpu_clk_session *session, int *event_fd);
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int nvgpu_clk_arb_install_request_fd(struct gk20a *g,
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struct nvgpu_clk_session *session, int *event_fd);
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void nvgpu_clk_arb_schedule_vf_table_update(struct gk20a *g);
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int nvgpu_clk_arb_get_current_pstate(struct gk20a *g);
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void nvgpu_clk_arb_pstate_change_lock(struct gk20a *g, bool lock);
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#endif /* _CLK_ARB_H_ */
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