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git://nv-tegra.nvidia.com/linux-nvgpu.git
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5ec241a1d8
On safety nonstall interrupt is not used and should be compiled out to rule out any chance of interference with safety code. Remove top handler support of nonstall interrupt for safety which is currently not applicable to linux. Jira NVGPU-7066 Jira NVGPU-4078 Change-Id: I278efc8da6ddd0f22c128af6630cfd1b20ba4784 Signed-off-by: Shashank Singh <shashsingh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2589006 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2671586 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
122 lines
2.9 KiB
C
122 lines
2.9 KiB
C
/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/kmem.h>
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#include <nvgpu/log.h>
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#include <nvgpu/cic_rm.h>
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#include "cic_rm_priv.h"
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int nvgpu_cic_rm_setup(struct gk20a *g)
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{
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struct nvgpu_cic_rm *cic_rm;
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int err = 0;
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if (g->cic_rm != NULL) {
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cic_dbg(g, "CIC_RM already initialized");
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return 0;
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}
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cic_rm = nvgpu_kzalloc(g, sizeof(*cic_rm));
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if (cic_rm == NULL) {
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nvgpu_err(g, "Failed to allocate memory "
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"for struct nvgpu_cic_rm");
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return -ENOMEM;
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}
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g->cic_rm = cic_rm;
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cic_dbg(g, "CIC_RM unit initialization done.");
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return err;
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}
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int nvgpu_cic_rm_init_vars(struct gk20a *g)
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{
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struct nvgpu_cic_rm *cic_rm;
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int err = 0;
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cic_rm = g->cic_rm;
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if (cic_rm == NULL) {
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nvgpu_err(g, "CIC_RM setup pending");
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return -EINVAL;
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}
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err = nvgpu_cond_init(&cic_rm->sw_irq_stall_last_handled_cond);
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if (err != 0) {
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nvgpu_err(g, "sw irq stall cond init failed\n");
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goto cleanup;
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}
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#ifdef CONFIG_NVGPU_NONSTALL_INTR
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err = nvgpu_cond_init(&cic_rm->sw_irq_nonstall_last_handled_cond);
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if (err != 0) {
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nvgpu_err(g, "sw irq nonstall cond init failed\n");
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goto cleanup_cond;
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}
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#endif
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return 0;
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#ifdef CONFIG_NVGPU_NONSTALL_INTR
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cleanup_cond:
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nvgpu_cond_destroy(&cic_rm->sw_irq_stall_last_handled_cond);
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#endif
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cleanup:
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return err;
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}
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int nvgpu_cic_rm_deinit_vars(struct gk20a *g)
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{
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struct nvgpu_cic_rm *cic_rm;
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cic_rm = g->cic_rm;
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if (cic_rm == NULL) {
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cic_dbg(g, "CIC_RM already removed");
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return 0;
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}
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nvgpu_cond_destroy(&cic_rm->sw_irq_stall_last_handled_cond);
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#ifdef CONFIG_NVGPU_NONSTALL_INTR
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nvgpu_cond_destroy(&cic_rm->sw_irq_nonstall_last_handled_cond);
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#endif
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return 0;
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}
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int nvgpu_cic_rm_remove(struct gk20a *g)
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{
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struct nvgpu_cic_rm *cic_rm;
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cic_rm = g->cic_rm;
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if (cic_rm == NULL) {
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cic_dbg(g, "CIC_RM already removed");
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return 0;
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}
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nvgpu_kfree(g, cic_rm);
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g->cic_rm = NULL;
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return 0;
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}
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