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c1a995403a
-Add check for ECC parity errors in IMEM, DMEM, EMEM, DCLS, REG for ACR running in GSP engine. The EXTIRQ3 external interrupt is set from ACR pointing towards host. -Add function to check error type when ACR or Bootrom execution fails and report accordingly to SDL with relevant error codes. This is a part of HSI safety requirements. Bug 3564039 Jira NVGPU-8108 Change-Id: I65407371f7a1d1ba50a10bdf443ef6b903eeaa36 Signed-off-by: mpoojary <mpoojary@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2678100 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
55 lines
2.3 KiB
C
55 lines
2.3 KiB
C
/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef GSP_GA10B_H
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#define GSP_GA10B_H
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u32 ga10b_gsp_falcon_base_addr(void);
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u32 ga10b_gsp_falcon2_base_addr(void);
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int ga10b_gsp_engine_reset(struct gk20a *g);
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bool ga10b_gsp_validate_mem_integrity(struct gk20a *g);
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#ifdef CONFIG_NVGPU_GSP_SCHEDULER
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void ga10b_gsp_flcn_setup_boot_config(struct gk20a *g);
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/* queue */
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u32 ga10b_gsp_queue_head_r(u32 i);
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u32 ga10b_gsp_queue_head__size_1_v(void);
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u32 ga10b_gsp_queue_tail_r(u32 i);
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u32 ga10b_gsp_queue_tail__size_1_v(void);
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int ga10b_gsp_queue_head(struct gk20a *g, u32 queue_id, u32 queue_index,
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u32 *head, bool set);
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int ga10b_gsp_queue_tail(struct gk20a *g, u32 queue_id, u32 queue_index,
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u32 *tail, bool set);
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void ga10b_gsp_msgq_tail(struct gk20a *g, struct nvgpu_gsp *gsp,
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u32 *tail, bool set);
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int ga10b_gsp_flcn_copy_to_emem(struct gk20a *g,
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u32 dst, u8 *src, u32 size, u8 port);
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int ga10b_gsp_flcn_copy_from_emem(struct gk20a *g,
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u32 src, u8 *dst, u32 size, u8 port);
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/* interrupt */
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void ga10b_gsp_enable_irq(struct gk20a *g, bool enable);
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void ga10b_gsp_isr(struct gk20a *g, struct nvgpu_gsp *gsp);
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void ga10b_gsp_set_msg_intr(struct gk20a *g);
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#endif /* CONFIG_NVGPU_GSP_SCHEDULER */
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#endif /* GSP_GA10B_H */
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