mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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e81a36e56a
It's preparing to add bellow CFLAGS:
-Werror -Wall -Wextra \
-Wmissing-braces -Wpointer-arith -Wundef \
-Wconversion -Wsign-conversion \
-Wformat-security \
-Wmissing-declarations -Wredundant-decls -Wimplicit-fallthrough
Jira GVSCI-11640
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: Ia16ef186da1e97badff9dd0bf8cbd6700dd77b15
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2555057
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
136 lines
4.2 KiB
C
136 lines
4.2 KiB
C
/*
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* GM20B L2
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*
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* Copyright (c) 2014-2020 NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/trace.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/ltc.h>
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#include <nvgpu/fbp.h>
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#include <nvgpu/io.h>
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#include <nvgpu/utils.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/static_analysis.h>
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#include <nvgpu/hw/gm20b/hw_ltc_gm20b.h>
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#include "ltc_gm20b.h"
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#ifdef CONFIG_NVGPU_DEBUGGER
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/*
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* LTC pri addressing
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*/
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bool gm20b_ltc_pri_is_ltc_addr(struct gk20a *g, u32 addr)
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{
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(void)g;
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return ((addr >= ltc_pltcg_base_v()) && (addr < ltc_pltcg_extent_v()));
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}
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bool gm20b_ltc_is_ltcs_ltss_addr(struct gk20a *g, u32 addr)
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{
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u32 ltc_shared_base = ltc_ltcs_ltss_v();
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u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
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if (addr >= ltc_shared_base) {
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return (addr < nvgpu_safe_add_u32(ltc_shared_base, lts_stride));
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}
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return false;
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}
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bool gm20b_ltc_is_ltcn_ltss_addr(struct gk20a *g, u32 addr)
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{
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u32 lts_shared_base = ltc_ltc0_ltss_v();
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u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
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u32 addr_mask = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE) - 1U;
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u32 base_offset = lts_shared_base & addr_mask;
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u32 end_offset = nvgpu_safe_add_u32(base_offset, lts_stride);
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return (!gm20b_ltc_is_ltcs_ltss_addr(g, addr)) &&
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((addr & addr_mask) >= base_offset) &&
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((addr & addr_mask) < end_offset);
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}
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static void gm20b_ltc_update_ltc_lts_addr(struct gk20a *g, u32 addr,
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u32 ltc_num, u32 *priv_addr_table, u32 *priv_addr_table_index)
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{
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u32 num_ltc_slices = g->ops.top.get_max_lts_per_ltc(g);
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u32 index = *priv_addr_table_index;
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u32 lts_num;
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u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
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u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
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for (lts_num = 0; lts_num < num_ltc_slices;
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lts_num = nvgpu_safe_add_u32(lts_num, 1U)) {
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priv_addr_table[index] = nvgpu_safe_add_u32(
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ltc_ltc0_lts0_v(),
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nvgpu_safe_add_u32(
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nvgpu_safe_add_u32(
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nvgpu_safe_mult_u32(ltc_num, ltc_stride),
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nvgpu_safe_mult_u32(lts_num, lts_stride)),
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(addr & nvgpu_safe_sub_u32(
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lts_stride, 1U))));
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index = nvgpu_safe_add_u32(index, 1U);
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}
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*priv_addr_table_index = index;
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}
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void gm20b_ltc_split_lts_broadcast_addr(struct gk20a *g, u32 addr,
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u32 *priv_addr_table,
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u32 *priv_addr_table_index)
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{
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u32 num_ltc = g->ltc->ltc_count;
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u32 i, start, ltc_num = 0;
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u32 pltcg_base = ltc_pltcg_base_v();
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u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
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for (i = 0; i < num_ltc; i++) {
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start = nvgpu_safe_add_u32(pltcg_base,
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nvgpu_safe_mult_u32(i, ltc_stride));
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if (addr >= start) {
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if (addr < nvgpu_safe_add_u32(start, ltc_stride)) {
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ltc_num = i;
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break;
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}
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}
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}
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gm20b_ltc_update_ltc_lts_addr(g, addr, ltc_num, priv_addr_table,
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priv_addr_table_index);
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}
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void gm20b_ltc_split_ltc_broadcast_addr(struct gk20a *g, u32 addr,
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u32 *priv_addr_table,
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u32 *priv_addr_table_index)
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{
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u32 num_ltc = g->ltc->ltc_count;
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u32 ltc_num;
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for (ltc_num = 0; ltc_num < num_ltc; ltc_num =
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nvgpu_safe_add_u32(ltc_num, 1U)) {
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gm20b_ltc_update_ltc_lts_addr(g, addr, ltc_num,
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priv_addr_table, priv_addr_table_index);
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}
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}
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#endif /* CONFIG_NVGPU_DEBUGGER */
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