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db30ea3362
Nvgpu does not support nested interrupts and as a result priv/pbus interrupt do not reach cpu while other interrupts on intr_0 (stall) tree are being processed. This issue is not specific to priv/pbus but since pbus errors are critical, it is important to detect it early on. Below is the snippet from one of the failing logs where nvgpu is doing recovery to process gr interrupt. Right after GR engine is reset (PGRAPH of PMC_ENABLE), failing priv accesses should have triggered pbus interrupt but it does not reach cpu until gr interrupt is handled. Any interrupt that requires recovery will take longer to finish isr as recovery is done as part of isr. Also intr_0 (stall) interrupts are paused while stall interrupt is being processed. gm20b_gr_falcon_bind_instblk:147 [ERR] arbiter idle timeout, status: badf1020 gm20b_gr_falcon_wait_for_fecs_arb_idle:125 [ERR] arbiter idle timeout, fecs ctxsw status: 0xbadf1020 Fix to detect pbus intr while other stall interrupts are being processed is to move pbus intr enable/disable/clear/handle to nonstall (intr_1) tree. Configure pbus_intr_en_1 to route pbus to nostall tree. Priv interrupts cannot be moved to nonstall (intr_1) tree due to h/w not supporting this. In Turing, moving pbus intr to nonstall is not feasible as mc_intr(1) tree is deprecated. Add Turing specific stall intr handler hals with original logic to route pbus intr to mc_intr(0). JIRA NVGPU-25 Bug 200603566 Change-Id: I36fc376800802f20a0ea581b4f787bcc6c73ec7e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2354192 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
69 lines
3.0 KiB
C
69 lines
3.0 KiB
C
/*
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* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_MC_TU104_H
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#define NVGPU_MC_TU104_H
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#include <nvgpu/types.h>
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#define NV_CPU_INTR_SUBTREE_TO_TOP_IDX(i) ((i) / 32U)
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#define NV_CPU_INTR_SUBTREE_TO_TOP_BIT(i) ((i) % 32U)
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#define NV_CPU_INTR_SUBTREE_TO_LEAF_REG0(i) ((i)*2U)
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#define NV_CPU_INTR_SUBTREE_TO_LEAF_REG1(i) (((i)*2U) + 1U)
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#define NV_CPU_INTR_GPU_VECTOR_TO_LEAF_REG(i) ((i) / 32U)
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#define NV_CPU_INTR_GPU_VECTOR_TO_LEAF_BIT(i) ((i) % 32U)
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#define NV_CPU_INTR_GPU_VECTOR_TO_SUBTREE(i) ((NV_CPU_INTR_GPU_VECTOR_TO_LEAF_REG(i)) / 2U)
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#define NV_CPU_INTR_TOP_NONSTALL_SUBTREE 0U
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struct gk20a;
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void intr_tu104_leaf_en_set(struct gk20a *g, u32 leaf_reg_index,
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u32 leaf_reg_bit);
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void intr_tu104_leaf_en_clear(struct gk20a *g, u32 leaf_reg_index,
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u32 leaf_reg_bit);
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void intr_tu104_top_en_set(struct gk20a *g, u32 top_reg_index,
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u32 top_reg_bit);
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void intr_tu104_vector_en_set(struct gk20a *g, u32 intr_vector);
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void intr_tu104_vector_en_clear(struct gk20a *g, u32 intr_vector);
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bool intr_tu104_vector_intr_pending(struct gk20a *g, u32 intr_vector);
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void intr_tu104_intr_clear_leaf_vector(struct gk20a *g, u32 intr_vector);
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void intr_tu104_stall_unit_config(struct gk20a *g, u32 unit, bool enable);
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void intr_tu104_nonstall_unit_config(struct gk20a *g, u32 unit, bool enable);
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void intr_tu104_mask(struct gk20a *g);
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u32 intr_tu104_stall(struct gk20a *g);
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void intr_tu104_stall_pause(struct gk20a *g);
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void intr_tu104_stall_resume(struct gk20a *g);
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u32 intr_tu104_nonstall(struct gk20a *g);
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void intr_tu104_nonstall_pause(struct gk20a *g);
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void intr_tu104_nonstall_resume(struct gk20a *g);
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u32 intr_tu104_isr_nonstall(struct gk20a *g);
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bool intr_tu104_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0);
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void intr_tu104_log_pending_intrs(struct gk20a *g);
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void mc_tu104_fbpa_isr(struct gk20a *g);
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void mc_tu104_ltc_isr(struct gk20a *g);
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void mc_tu104_isr_stall(struct gk20a *g);
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#endif /* NVGPU_MC_TU104_H */
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