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3e43f92f21
Mass copy ga10b & ga100 sources from nvgpu-next repo. TOP COMMIT-ID: 98f530e6924c844a1bf46816933a7fe015f3cce1 Jira NVGPU-4771 Change-Id: Ibf7102e9208133f8ef3bd3a98381138d5396d831 Signed-off-by: Sagar Kadamati <skadamati@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2524817 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
358 lines
6.7 KiB
C
358 lines
6.7 KiB
C
/*
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* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include "perf_ga100.h"
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#include <nvgpu/hw/ga100/hw_perf_ga100.h>
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static const u32 hwpm_sys_perfmon_regs[] =
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{
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/* This list is autogenerated. Do not edit. */
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0x00260000,
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0x00260004,
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0x00260008,
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0x0026000c,
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0x00260010,
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0x00260014,
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0x00260020,
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0x00260024,
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0x00260028,
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0x0026002c,
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0x00260030,
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0x00260034,
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0x00260040,
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0x00260044,
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0x00260048,
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0x0026004c,
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0x00260050,
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0x00260054,
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0x00260058,
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0x0026005c,
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0x00260060,
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0x00260064,
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0x00260068,
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0x0026006c,
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0x00260070,
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0x00260074,
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0x00260078,
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0x0026007c,
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0x00260080,
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0x00260084,
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0x00260088,
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0x0026008c,
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0x00260090,
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0x00260094,
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0x00260098,
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0x0026009c,
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0x002600a0,
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0x002600a4,
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0x002600a8,
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0x002600ac,
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0x002600b0,
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0x002600b4,
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0x002600b8,
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0x002600bc,
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0x002600c0,
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0x002600c4,
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0x002600c8,
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0x002600cc,
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0x002600d0,
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0x002600d4,
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0x002600d8,
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0x002600dc,
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0x002600e0,
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0x002600e4,
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0x002600e8,
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0x002600ec,
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0x002600f8,
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0x002600fc,
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0x00260104,
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0x00260108,
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0x0026010c,
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0x00260110,
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0x00260128,
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0x00260114,
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0x00260118,
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0x0026011c,
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0x00260124,
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0x00260130,
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0x00260100,
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};
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static const u32 hwpm_gpc_perfmon_regs[] =
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{
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/* This list is autogenerated. Do not edit. */
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0x00278000,
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0x00278004,
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0x00278008,
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0x0027800c,
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0x00278010,
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0x00278014,
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0x00278020,
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0x00278024,
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0x00278028,
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0x0027802c,
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0x00278030,
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0x00278034,
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0x00278040,
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0x00278044,
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0x00278048,
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0x0027804c,
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0x00278050,
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0x00278054,
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0x00278058,
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0x0027805c,
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0x00278060,
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0x00278064,
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0x00278068,
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0x0027806c,
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0x00278070,
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0x00278074,
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0x00278078,
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0x0027807c,
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0x00278080,
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0x00278084,
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0x00278088,
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0x0027808c,
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0x00278090,
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0x00278094,
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0x00278098,
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0x0027809c,
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0x002780a0,
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0x002780a4,
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0x002780a8,
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0x002780ac,
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0x002780b0,
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0x002780b4,
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0x002780b8,
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0x002780bc,
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0x002780c0,
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0x002780c4,
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0x002780c8,
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0x002780cc,
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0x002780d0,
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0x002780d4,
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0x002780d8,
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0x002780dc,
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0x002780e0,
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0x002780e4,
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0x002780e8,
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0x002780ec,
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0x002780f8,
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0x002780fc,
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0x00278104,
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0x00278108,
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0x0027810c,
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0x00278110,
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0x00278128,
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0x00278114,
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0x00278118,
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0x0027811c,
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0x00278124,
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0x00278130,
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0x00278100,
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};
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static const u32 hwpm_fbp_perfmon_regs[] =
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{
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/* This list is autogenerated. Do not edit. */
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0x0027c000,
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0x0027c004,
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0x0027c008,
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0x0027c00c,
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0x0027c010,
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0x0027c014,
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0x0027c020,
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0x0027c024,
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0x0027c028,
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0x0027c02c,
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0x0027c030,
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0x0027c034,
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0x0027c040,
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0x0027c044,
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0x0027c048,
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0x0027c04c,
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0x0027c050,
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0x0027c054,
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0x0027c058,
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0x0027c05c,
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0x0027c060,
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0x0027c064,
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0x0027c068,
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0x0027c06c,
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0x0027c070,
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0x0027c074,
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0x0027c078,
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0x0027c07c,
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0x0027c080,
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0x0027c084,
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0x0027c088,
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0x0027c08c,
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0x0027c090,
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0x0027c094,
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0x0027c098,
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0x0027c09c,
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0x0027c0a0,
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0x0027c0a4,
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0x0027c0a8,
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0x0027c0ac,
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0x0027c0b0,
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0x0027c0b4,
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0x0027c0b8,
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0x0027c0bc,
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0x0027c0c0,
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0x0027c0c4,
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0x0027c0c8,
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0x0027c0cc,
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0x0027c0d0,
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0x0027c0d4,
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0x0027c0d8,
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0x0027c0dc,
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0x0027c0e0,
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0x0027c0e4,
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0x0027c0e8,
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0x0027c0ec,
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0x0027c0f8,
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0x0027c0fc,
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0x0027c104,
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0x0027c108,
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0x0027c10c,
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0x0027c110,
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0x0027c128,
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0x0027c114,
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0x0027c118,
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0x0027c11c,
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0x0027c124,
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0x0027c130,
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0x0027c100,
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};
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const u32 *ga100_perf_get_hwpm_sys_perfmon_regs(u32 *count)
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{
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*count = sizeof(hwpm_sys_perfmon_regs) / sizeof(hwpm_sys_perfmon_regs[0]);
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return hwpm_sys_perfmon_regs;
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}
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const u32 *ga100_perf_get_hwpm_gpc_perfmon_regs(u32 *count)
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{
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*count = sizeof(hwpm_gpc_perfmon_regs) / sizeof(hwpm_gpc_perfmon_regs[0]);
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return hwpm_gpc_perfmon_regs;
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}
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const u32 *ga100_perf_get_hwpm_fbp_perfmon_regs(u32 *count)
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{
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*count = sizeof(hwpm_fbp_perfmon_regs) / sizeof(hwpm_fbp_perfmon_regs[0]);
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return hwpm_fbp_perfmon_regs;
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}
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u32 ga100_perf_get_pmmsys_per_chiplet_offset(void)
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{
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/*
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* No register to find the offset of pmmsys register.
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* Difference of pmmsys register address ranges plus 1 will provide
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* the offset
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*/
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u32 reg_offset = 1U;
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return (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + reg_offset);
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}
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u32 ga100_perf_get_pmmgpc_per_chiplet_offset(void)
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{
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/*
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* No register to find the offset of pmmgpc register.
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* Difference of pmmgpc register address ranges plus 1 will provide
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* the offset
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*/
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u32 reg_offset = 1U;
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return (perf_pmmgpc_extent_v() - perf_pmmgpc_base_v() + reg_offset);
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}
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u32 ga100_perf_get_pmmfbp_per_chiplet_offset(void)
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{
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/*
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* No register to find the offset of pmmfbp register.
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* Difference of pmmfbp register address ranges plus 1 will provide
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* the offset
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*/
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u32 reg_offset = 1U;
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return (perf_pmmfbp_extent_v() - perf_pmmfbp_base_v() + reg_offset);
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}
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void ga100_perf_get_num_hwpm_perfmon(struct gk20a *g, u32 *num_sys_perfmon,
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u32 *num_fbp_perfmon, u32 *num_gpc_perfmon)
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{
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int err;
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u32 buf_offset_lo, buf_offset_addr, num_offsets;
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u32 perfmon_index = 0U;
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u32 max_offsets = 1U;
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for (perfmon_index = 0U; perfmon_index <
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perf_pmmsys_engine_sel__size_1_v();
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perfmon_index++) {
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err = g->ops.gr.get_pm_ctx_buffer_offsets(g,
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perf_pmmsys_engine_sel_r(perfmon_index),
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max_offsets,
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&buf_offset_lo,
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&buf_offset_addr,
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&num_offsets);
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if (err != 0U) {
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break;
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}
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}
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*num_sys_perfmon = perfmon_index;
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for (perfmon_index = 0U; perfmon_index <
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perf_pmmfbp_engine_sel__size_1_v();
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perfmon_index++) {
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err = g->ops.gr.get_pm_ctx_buffer_offsets(g,
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perf_pmmfbp_engine_sel_r(perfmon_index),
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max_offsets,
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&buf_offset_lo,
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&buf_offset_addr,
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&num_offsets);
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if (err != 0U) {
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break;
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}
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}
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*num_fbp_perfmon = perfmon_index;
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for (perfmon_index = 0U; perfmon_index <
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perf_pmmgpc_engine_sel__size_1_v();
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perfmon_index++) {
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err = g->ops.gr.get_pm_ctx_buffer_offsets(g,
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perf_pmmgpc_engine_sel_r(perfmon_index),
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max_offsets,
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&buf_offset_lo,
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&buf_offset_addr,
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&num_offsets);
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if (err != 0U) {
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break;
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}
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}
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*num_gpc_perfmon = perfmon_index;
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}
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