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810317fadc
pmuif structures refer to the ctrl structures, so that means that ctrl structures are part of the pmuif. Move the headers to the right place and update all include statements to include from the right place. JIRA NVGPU-596 Change-Id: I7be1a727be654d58eccd0e12d599979687dd0733 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1934022 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
70 lines
2.3 KiB
C
70 lines
2.3 KiB
C
/*
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* general power channel structures & definitions
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*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_PMGR_PWRMONITOR_H
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#define NVGPU_PMGR_PWRMONITOR_H
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#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
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#include <nvgpu/boardobjgrp.h>
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#include <nvgpu/boardobj.h>
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#include <nvgpu/pmuif/ctrlpmgr.h>
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struct pwr_channel {
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struct boardobj super;
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u8 pwr_rail;
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u32 volt_fixed_uv;
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u32 pwr_corr_slope;
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s32 pwr_corr_offset_mw;
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u32 curr_corr_slope;
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s32 curr_corr_offset_ma;
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u32 dependent_ch_mask;
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};
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struct pwr_chrelationship {
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struct boardobj super;
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u8 chIdx;
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};
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struct pwr_channel_sensor {
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struct pwr_channel super;
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u8 pwr_dev_idx;
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u8 pwr_dev_prov_idx;
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};
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struct pmgr_pwr_monitor {
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bool b_is_topology_tbl_ver_1x;
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struct boardobjgrp_e32 pwr_channels;
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struct boardobjgrp_e32 pwr_ch_rels;
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u8 total_gpu_channel_idx;
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u32 physical_channel_mask;
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struct nv_pmu_pmgr_pwr_monitor_pack pmu_data;
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};
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#define PMGR_PWR_MONITOR_GET_PWR_CHANNEL(g, channel_idx) \
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((struct pwr_channel *)BOARDOBJGRP_OBJ_GET_BY_IDX( \
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&(g->pmgr_pmu.pmgr_monitorobjs.pwr_channels.super), (channel_idx)))
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int pmgr_monitor_sw_setup(struct gk20a *g);
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#endif /* NVGPU_PMGR_PWRMONITOR_H */
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