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a47ce8eafe
This is adding ipa-pa cache for HV-qnx by making the code as OS independant. NVGPU-7329 Change-Id: If003ddf323124ba0899d7ead5db5c5478ddfc6e0 Signed-off-by: Dinesh T <dt@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2645771 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
97 lines
3.0 KiB
C
97 lines
3.0 KiB
C
/*
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/ipa_pa_cache.h>
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static u64 nvgpu_ipa_to_pa_cache_lookup(struct gk20a *g, u64 ipa,
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u64 *pa_len)
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{
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struct nvgpu_ipa_desc *desc;
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struct nvgpu_ipa_pa_cache *ipa_cache;
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u32 i = 0U;
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u64 pa = 0UL;
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ipa_cache = &(g->ipa_pa_cache);
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desc = &(ipa_cache->ipa[0]);
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for (i = 0; i < ipa_cache->num_ipa_desc; ++i, ++desc) {
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if (ipa >= desc->ipa_base &&
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(ipa < (desc->ipa_base + desc->ipa_size))) {
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pa = ipa - desc->ipa_base + desc->pa_base;
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if (pa_len != NULL) {
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*pa_len = desc->ipa_size -(ipa - desc->ipa_base);
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}
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return pa;
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}
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}
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return 0U;
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}
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u64 nvgpu_ipa_to_pa_cache_lookup_locked(struct gk20a *g, u64 ipa,
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u64 *pa_len)
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{
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struct nvgpu_ipa_pa_cache *ipa_cache;
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u64 pa = 0UL;
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ipa_cache = &(g->ipa_pa_cache);
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nvgpu_rwsem_down_read(&(ipa_cache->ipa_pa_rw_lock));
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pa = nvgpu_ipa_to_pa_cache_lookup(g, ipa, pa_len);
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nvgpu_rwsem_up_read(&(ipa_cache->ipa_pa_rw_lock));
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return pa;
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}
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void nvgpu_ipa_to_pa_add_to_cache(struct gk20a *g, u64 ipa, u64 pa,
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struct nvgpu_hyp_ipa_pa_info *info)
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{
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struct nvgpu_ipa_pa_cache *ipa_cache;
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struct nvgpu_ipa_desc *desc = NULL;
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u64 pa_cached = 0U;
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ipa_cache = &(g->ipa_pa_cache);
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nvgpu_rwsem_down_write(&(ipa_cache->ipa_pa_rw_lock));
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pa_cached = nvgpu_ipa_to_pa_cache_lookup(g, ipa, NULL);
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if (pa_cached != 0UL) {
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/* Check any other context insert the translation
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* already and return.
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*/
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nvgpu_assert(pa_cached == pa);
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nvgpu_rwsem_up_write(&(ipa_cache->ipa_pa_rw_lock));
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return;
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}
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if (ipa_cache->num_ipa_desc >= MAX_IPA_PA_CACHE) {
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desc = &ipa_cache->ipa[nvgpu_current_time_ns() %
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MAX_IPA_PA_CACHE];
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} else {
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desc = &ipa_cache->ipa[ipa_cache->num_ipa_desc++];
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}
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desc->ipa_base = ipa - info->offset;
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desc->ipa_size = info->size;
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desc->pa_base = info->base;
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nvgpu_rwsem_up_write(&(ipa_cache->ipa_pa_rw_lock));
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}
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