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fe27a7f934
gr_gk20a_update_hwpm_ctxsw_mode() right now validates the incoming
hwpm mode, checks if it is already set, and if not, it will go ahead
and set the new hwpm mode by calling g->ops.gr.ctxsw_prog HALs
Instead of programming hwpm mode in gr_gk20a.c, move the programming
to gr/ctx and gr/subctx units by adding below APIs
nvgpu_gr_ctx_prepare_hwpm_mode() - validate the incoming mode and
check if it is already set
nvgpu_gr_ctx_set_hwpm_mode() - set pm mode in graphics context
nvgpu_gr_subctx_set_hwpm_mode() - set pm mode in subcontext
Add gpu_va field to struct pm_ctx_desc to store the gpu_va to be
programmed into context
Rename NVGPU_DBG_HWPM_CTXSW_MODE_* to NVGPU_GR_CTX_HWPM_CTXSW_MODE_*
and move them to gr/ctx.h
Remove below HALs since they are no longer used
g->ops.gr.ctxsw_prog.set_pm_mode_no_ctxsw()
g->ops.gr.ctxsw_prog.set_pm_mode_ctxsw()
g->ops.gr.ctxsw_prog.set_pm_mode_stream_out_ctxsw()
Jira NVGPU-1527
Jira NVGPU-1613
Change-Id: Id2a4d498182ec0e3586dc7265f73a25870ca2ef7
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011093
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
138 lines
4.2 KiB
C
138 lines
4.2 KiB
C
/*
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* Tegra GK20A GPU Debugger Driver
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*
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* Copyright (c) 2013-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_DEBUGGER_H
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#define NVGPU_DEBUGGER_H
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#include <nvgpu/cond.h>
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#include <nvgpu/lock.h>
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#include <nvgpu/list.h>
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struct gk20a;
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struct channel_gk20a;
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struct dbg_session_gk20a;
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struct channel_gk20a *
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nvgpu_dbg_gpu_get_session_channel(struct dbg_session_gk20a *dbg_s);
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struct dbg_gpu_session_events {
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struct nvgpu_cond wait_queue;
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bool events_enabled;
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int num_pending_events;
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};
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struct dbg_session_gk20a {
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/* dbg session id used for trace/prints */
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int id;
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/* profiler session, if any */
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bool is_profiler;
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/* has a valid profiler reservation */
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bool has_profiler_reservation;
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/* power enabled or disabled */
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bool is_pg_disabled;
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/* timeouts enabled or disabled */
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bool is_timeout_disabled;
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struct gk20a *g;
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/* list of bound channels, if any */
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struct nvgpu_list_node ch_list;
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struct nvgpu_mutex ch_list_lock;
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/* event support */
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struct dbg_gpu_session_events dbg_events;
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bool broadcast_stop_trigger;
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struct nvgpu_mutex ioctl_lock;
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};
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struct dbg_session_data {
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struct dbg_session_gk20a *dbg_s;
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struct nvgpu_list_node dbg_s_entry;
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};
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static inline struct dbg_session_data *
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dbg_session_data_from_dbg_s_entry(struct nvgpu_list_node *node)
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{
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return (struct dbg_session_data *)
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((uintptr_t)node - offsetof(struct dbg_session_data, dbg_s_entry));
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};
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struct dbg_session_channel_data {
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int channel_fd;
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u32 chid;
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struct nvgpu_list_node ch_entry;
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struct dbg_session_data *session_data;
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int (*unbind_single_channel)(struct dbg_session_gk20a *dbg_s,
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struct dbg_session_channel_data *ch_data);
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};
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static inline struct dbg_session_channel_data *
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dbg_session_channel_data_from_ch_entry(struct nvgpu_list_node *node)
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{
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return (struct dbg_session_channel_data *)
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((uintptr_t)node - offsetof(struct dbg_session_channel_data, ch_entry));
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};
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struct dbg_profiler_object_data {
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int session_id;
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u32 prof_handle;
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struct channel_gk20a *ch;
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bool has_reservation;
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struct nvgpu_list_node prof_obj_entry;
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};
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static inline struct dbg_profiler_object_data *
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dbg_profiler_object_data_from_prof_obj_entry(struct nvgpu_list_node *node)
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{
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return (struct dbg_profiler_object_data *)
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((uintptr_t)node - offsetof(struct dbg_profiler_object_data, prof_obj_entry));
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};
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/* used by the interrupt handler to post events */
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void nvgpu_dbg_gpu_post_events(struct channel_gk20a *ch);
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bool nvgpu_dbg_gpu_broadcast_stop_trigger(struct channel_gk20a *ch);
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void nvgpu_dbg_gpu_clear_broadcast_stop_trigger(struct channel_gk20a *ch);
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int nvgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s, bool disable_powergate);
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bool nvgpu_check_and_set_global_reservation(
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struct dbg_session_gk20a *dbg_s,
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struct dbg_profiler_object_data *prof_obj);
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bool nvgpu_check_and_set_context_reservation(
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struct dbg_session_gk20a *dbg_s,
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struct dbg_profiler_object_data *prof_obj);
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void nvgpu_release_profiler_reservation(struct dbg_session_gk20a *dbg_s,
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struct dbg_profiler_object_data *prof_obj);
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void nvgpu_dbg_session_post_event(struct dbg_session_gk20a *dbg_s);
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u32 nvgpu_set_powergate_locked(struct dbg_session_gk20a *dbg_s,
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bool mode);
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#endif /* NVGPU_DEBUGGER_H */
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