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9457a5ea91
The ccsr_channel_eng_faulted field exists from Volta onwards. Implement the read_state HAL op for those chips, and store that bit as a boolean in the channel state info. Jira NVGPU-1307 Change-Id: Ie997892f2d3db0725496661a4d3083e7396894cc Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2017267 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
49 lines
1.7 KiB
C
49 lines
1.7 KiB
C
/*
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* fifo common definitions (gr host)
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*
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* Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_FIFO_COMMON_H
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#define NVGPU_FIFO_COMMON_H
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#define RC_TYPE_NO_RC 0U
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#define RC_TYPE_MMU_FAULT 1U
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#define RC_TYPE_PBDMA_FAULT 2U
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#define RC_TYPE_GR_FAULT 3U
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#define RC_TYPE_PREEMPT_TIMEOUT 4U
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#define RC_TYPE_CTXSW_TIMEOUT 5U
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#define RC_TYPE_RUNLIST_UPDATE_TIMEOUT 6U
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#define RC_TYPE_FORCE_RESET 7U
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#define RC_TYPE_SCHED_ERR 8U
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struct nvgpu_channel_hw_state {
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bool enabled;
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bool next;
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bool ctx_reload;
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bool busy;
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bool pending_acquire;
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bool eng_faulted;
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const char *status_string;
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};
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#endif /* NVGPU_FIFO_COMMON_H */
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