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9346b104d4
Created sub-unit for ltc interrupt handling. Following 2-hals are moved from ltc to ltc intr unit: void (*isr)(struct gk20a *g, u32 ltc); void (*en_illegal_compstat)(struct gk20a *g, bool enable) Added new hal in ltc intr sub-unit for configuring ltc interrupts: void (*configure)(struct gk20a *g); Moved ltc interrupt related code from ltc to ltc intr unit. Chip ltc.intr hals are populated with updated function names created in ltc intr unit. Converted all "unsigned int" usage to "u32" in ltc and ltc intr units to match with hardware 32 bit register read/write. JIRA NVGPU-3042 JIRA NVGPU-2044 Change-Id: I8684dfcc8ae343e4588b93f2b0ccde0e227635df Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2081140 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>