mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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a8587d5ee3
Rename gr_idle_timeout_default to poll_timeout_default Rename NVGPU_DEFAULT_GR_IDLE_TIMEOUT to NVGPU_DEFAULT_POLL_TIMEOUT_MS Rename gk20a_get_gr_idle_timeout to nvgpu_get_poll_timeout JIRA NVGPU-1313 Change-Id: I17314f0fa4a386f806f6940073649a9082ee21ad Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2083130 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
243 lines
7.2 KiB
C
243 lines
7.2 KiB
C
/*
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* GP10B PMU
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*
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* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/pmu.h>
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#include <nvgpu/log.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/bug.h>
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#include "common/pmu/pmu_gp10b.h"
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#include "pmu_gk20a.h"
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#include <nvgpu/hw/gp10b/hw_pwr_gp10b.h>
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/* PROD settings for ELPG sequencing registers*/
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static struct pg_init_sequence_list _pginitseq_gp10b[] = {
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{0x0010ab10U, 0x0000868BU} ,
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{0x0010e118U, 0x8590848FU} ,
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{0x0010e000U, 0x0U} ,
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{0x0010e06cU, 0x000000A3U} ,
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{0x0010e06cU, 0x000000A0U} ,
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{0x0010e06cU, 0x00000095U} ,
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{0x0010e06cU, 0x000000A6U} ,
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{0x0010e06cU, 0x0000008CU} ,
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{0x0010e06cU, 0x00000080U} ,
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{0x0010e06cU, 0x00000081U} ,
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{0x0010e06cU, 0x00000087U} ,
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{0x0010e06cU, 0x00000088U} ,
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{0x0010e06cU, 0x0000008DU} ,
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{0x0010e06cU, 0x00000082U} ,
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{0x0010e06cU, 0x00000083U} ,
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{0x0010e06cU, 0x00000089U} ,
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{0x0010e06cU, 0x0000008AU} ,
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{0x0010e06cU, 0x000000A2U} ,
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{0x0010e06cU, 0x00000097U} ,
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{0x0010e06cU, 0x00000092U} ,
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{0x0010e06cU, 0x00000099U} ,
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{0x0010e06cU, 0x0000009BU} ,
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{0x0010e06cU, 0x0000009DU} ,
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{0x0010e06cU, 0x0000009FU} ,
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{0x0010e06cU, 0x000000A1U} ,
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{0x0010e06cU, 0x00000096U} ,
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{0x0010e06cU, 0x00000091U} ,
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{0x0010e06cU, 0x00000098U} ,
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{0x0010e06cU, 0x0000009AU} ,
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{0x0010e06cU, 0x0000009CU} ,
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{0x0010e06cU, 0x0000009EU} ,
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{0x0010ab14U, 0x00000000U} ,
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{0x0010e024U, 0x00000000U} ,
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{0x0010e028U, 0x00000000U} ,
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{0x0010e11cU, 0x00000000U} ,
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{0x0010ab1cU, 0x140B0BFFU} ,
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{0x0010e020U, 0x0E2626FFU} ,
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{0x0010e124U, 0x251010FFU} ,
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{0x0010ab20U, 0x89abcdefU} ,
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{0x0010ab24U, 0x00000000U} ,
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{0x0010e02cU, 0x89abcdefU} ,
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{0x0010e030U, 0x00000000U} ,
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{0x0010e128U, 0x89abcdefU} ,
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{0x0010e12cU, 0x00000000U} ,
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{0x0010ab28U, 0x7FFFFFFFU} ,
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{0x0010ab2cU, 0x70000000U} ,
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{0x0010e034U, 0x7FFFFFFFU} ,
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{0x0010e038U, 0x70000000U} ,
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{0x0010e130U, 0x7FFFFFFFU} ,
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{0x0010e134U, 0x70000000U} ,
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{0x0010ab30U, 0x00000000U} ,
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{0x0010ab34U, 0x00000001U} ,
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{0x00020004U, 0x00000000U} ,
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{0x0010e138U, 0x00000000U} ,
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{0x0010e040U, 0x00000000U} ,
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{0x0010e168U, 0x00000000U} ,
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{0x0010e114U, 0x0000A5A4U} ,
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{0x0010e110U, 0x00000000U} ,
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{0x0010e10cU, 0x8590848FU} ,
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{0x0010e05cU, 0x00000000U} ,
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{0x0010e044U, 0x00000000U} ,
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{0x0010a644U, 0x0000868BU} ,
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{0x0010a648U, 0x00000000U} ,
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{0x0010a64cU, 0x00829493U} ,
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{0x0010a650U, 0x00000000U} ,
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{0x0010e000U, 0x0U} ,
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{0x0010e068U, 0x000000A3U} ,
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{0x0010e068U, 0x000000A0U} ,
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{0x0010e068U, 0x00000095U} ,
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{0x0010e068U, 0x000000A6U} ,
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{0x0010e068U, 0x0000008CU} ,
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{0x0010e068U, 0x00000080U} ,
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{0x0010e068U, 0x00000081U} ,
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{0x0010e068U, 0x00000087U} ,
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{0x0010e068U, 0x00000088U} ,
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{0x0010e068U, 0x0000008DU} ,
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{0x0010e068U, 0x00000082U} ,
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{0x0010e068U, 0x00000083U} ,
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{0x0010e068U, 0x00000089U} ,
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{0x0010e068U, 0x0000008AU} ,
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{0x0010e068U, 0x000000A2U} ,
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{0x0010e068U, 0x00000097U} ,
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{0x0010e068U, 0x00000092U} ,
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{0x0010e068U, 0x00000099U} ,
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{0x0010e068U, 0x0000009BU} ,
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{0x0010e068U, 0x0000009DU} ,
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{0x0010e068U, 0x0000009FU} ,
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{0x0010e068U, 0x000000A1U} ,
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{0x0010e068U, 0x00000096U} ,
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{0x0010e068U, 0x00000091U} ,
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{0x0010e068U, 0x00000098U} ,
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{0x0010e068U, 0x0000009AU} ,
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{0x0010e068U, 0x0000009CU} ,
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{0x0010e068U, 0x0000009EU} ,
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{0x0010e000U, 0x0U} ,
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{0x0010e004U, 0x0000008EU},
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};
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static void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask,
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u32 flags)
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{
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struct nvgpu_pmu *pmu = &g->pmu;
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struct pmu_cmd cmd;
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u32 seq;
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size_t tmp_size;
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nvgpu_log_fn(g, " ");
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nvgpu_pmu_dbg(g, "wprinit status = %x", g->pmu_lsf_pmu_wpr_init_done);
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if (g->pmu_lsf_pmu_wpr_init_done) {
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/* send message to load FECS falcon */
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(void) memset(&cmd, 0, sizeof(struct pmu_cmd));
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cmd.hdr.unit_id = PMU_UNIT_ACR;
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tmp_size = PMU_CMD_HDR_SIZE +
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sizeof(struct pmu_acr_cmd_bootstrap_multiple_falcons);
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nvgpu_assert(tmp_size <= (size_t)U8_MAX);
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cmd.hdr.size = (u8)tmp_size;
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cmd.cmd.acr.boot_falcons.cmd_type =
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PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS;
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cmd.cmd.acr.boot_falcons.flags = flags;
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cmd.cmd.acr.boot_falcons.falconidmask =
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falconidmask;
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cmd.cmd.acr.boot_falcons.usevamask = 0;
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cmd.cmd.acr.boot_falcons.wprvirtualbase.lo = 0x0U;
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cmd.cmd.acr.boot_falcons.wprvirtualbase.hi = 0x0U;
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nvgpu_pmu_dbg(g, "PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS:%x",
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falconidmask);
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nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
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pmu_handle_fecs_boot_acr_msg, pmu, &seq);
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}
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nvgpu_log_fn(g, "done");
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return;
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}
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int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
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{
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u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES;
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/* GM20B PMU supports loading FECS and GPCCS only */
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if (falconidmask == 0U) {
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return -EINVAL;
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}
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if ((falconidmask &
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~(BIT32(FALCON_ID_FECS) |
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BIT32(FALCON_ID_GPCCS))) != 0U) {
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return -EINVAL;
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}
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g->pmu_lsf_loaded_falcon_id = 0;
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/* check whether pmu is ready to bootstrap lsf if not wait for it */
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if (!g->pmu_lsf_pmu_wpr_init_done) {
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pmu_wait_message_cond(&g->pmu,
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nvgpu_get_poll_timeout(g),
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&g->pmu_lsf_pmu_wpr_init_done, 1);
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/* check again if it still not ready indicate an error */
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if (!g->pmu_lsf_pmu_wpr_init_done) {
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nvgpu_err(g, "PMU not ready to load LSF");
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return -ETIMEDOUT;
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}
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}
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/* load falcon(s) */
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gp10b_pmu_load_multiple_falcons(g, falconidmask, flags);
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nvgpu_assert(falconidmask <= U8_MAX);
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pmu_wait_message_cond(&g->pmu,
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nvgpu_get_poll_timeout(g),
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&g->pmu_lsf_loaded_falcon_id, (u8)falconidmask);
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if (g->pmu_lsf_loaded_falcon_id != falconidmask) {
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return -ETIMEDOUT;
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}
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return 0;
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}
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int gp10b_pmu_setup_elpg(struct gk20a *g)
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{
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int ret = 0;
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size_t reg_writes;
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size_t index;
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nvgpu_log_fn(g, " ");
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if (g->can_elpg && g->elpg_enabled) {
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reg_writes = ARRAY_SIZE(_pginitseq_gp10b);
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/* Initialize registers with production values*/
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for (index = 0; index < reg_writes; index++) {
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gk20a_writel(g, _pginitseq_gp10b[index].regaddr,
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_pginitseq_gp10b[index].writeval);
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}
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}
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nvgpu_log_fn(g, "done");
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return ret;
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}
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void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr)
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{
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gk20a_writel(g, pwr_falcon_dmatrfbase_r(),
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addr);
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gk20a_writel(g, pwr_falcon_dmatrfbase1_r(),
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0x0U);
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}
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bool gp10b_is_pmu_supported(struct gk20a *g)
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{
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return true;
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}
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