mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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e943e6278a
This patch does the following. 1. Remove unused functions from volt_pmu.c. 2. Append public functions with nvgpu. 3. Remove GP106 functions and rename TU104 to generic functions. 4. Rename volt struct from gpu_ops. 5. Remove the unused volt.h header file. 6. Make local functions as static and put in order. 7. Remove unused inclusion on header files. 8. After 4, generic functions can be called directly instead of g->ops. Jira NVGPU-1956 Change-Id: Icaea0ca817d37cccfc09241baa2f047ec2688169 Signed-off-by: Abdul Salam <absalam@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2076535 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
140 lines
4.1 KiB
C
140 lines
4.1 KiB
C
/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/pmu.h>
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#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/boardobjgrp.h>
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#include <nvgpu/boardobjgrp_e32.h>
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#include <nvgpu/pmuif/ctrlvolt.h>
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#include <nvgpu/pmuif/ctrlperf.h>
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#include <nvgpu/string.h>
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#include <nvgpu/pmu/perf.h>
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#include <nvgpu/pmu/volt.h>
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#include "volt_pmu.h"
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struct volt_rpc_pmucmdhandler_params {
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struct nv_pmu_volt_rpc *prpc_call;
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u32 success;
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};
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static int volt_set_voltage_rpc(struct gk20a *g, u8 client_id,
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struct ctrl_volt_volt_rail_list_v1 *prail_list)
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{
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struct nvgpu_pmu *pmu = &g->pmu;
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struct nv_pmu_rpc_struct_volt_volt_set_voltage rpc;
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int status = 0;
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(void) memset(&rpc, 0,
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sizeof(struct nv_pmu_rpc_struct_volt_volt_set_voltage));
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rpc.client_id = 0x1;
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rpc.rail_list = *prail_list;
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PMU_RPC_EXECUTE_CPB(status, pmu, VOLT, VOLT_SET_VOLTAGE, &rpc, 0);
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if (status != 0) {
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nvgpu_err(g, "Failed to execute RPC status=0x%x",
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status);
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}
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return status;
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}
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static int volt_rail_get_voltage(struct gk20a *g,
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u8 volt_domain, u32 *pvoltage_uv)
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{
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struct nvgpu_pmu *pmu = &g->pmu;
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struct nv_pmu_rpc_struct_volt_volt_rail_get_voltage rpc;
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int status = 0;
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u8 rail_idx;
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rail_idx = nvgpu_volt_rail_volt_domain_convert_to_idx(g, volt_domain);
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if ((rail_idx == CTRL_VOLT_RAIL_INDEX_INVALID) ||
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(!VOLT_RAIL_INDEX_IS_VALID(&g->perf_pmu->volt, rail_idx))) {
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nvgpu_err(g,
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"failed: volt_domain = %d, voltage rail table = %d.",
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volt_domain, rail_idx);
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return -EINVAL;
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}
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(void) memset(&rpc, 0,
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sizeof(struct nv_pmu_rpc_struct_volt_volt_rail_get_voltage));
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rpc.rail_idx = rail_idx;
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PMU_RPC_EXECUTE_CPB(status, pmu, VOLT, VOLT_RAIL_GET_VOLTAGE, &rpc, 0);
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if (status != 0) {
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nvgpu_err(g, "Failed to execute RPC status=0x%x",
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status);
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}
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*pvoltage_uv = rpc.voltage_uv;
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return status;
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}
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static int volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv,
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u32 sram_voltage_uv)
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{
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int status = 0;
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struct ctrl_volt_volt_rail_list_v1 rail_list = { 0 };
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rail_list.num_rails = RAIL_COUNT_GV;
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rail_list.rails[0].rail_idx =
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nvgpu_volt_rail_volt_domain_convert_to_idx(g,
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CTRL_VOLT_DOMAIN_LOGIC);
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rail_list.rails[0].voltage_uv = logic_voltage_uv;
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rail_list.rails[0].voltage_min_noise_unaware_uv = logic_voltage_uv;
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status = volt_set_voltage_rpc(g,
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CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ, &rail_list);
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return status;
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}
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int nvgpu_volt_send_load_cmd_to_pmu(struct gk20a *g)
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{
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struct nvgpu_pmu *pmu = &g->pmu;
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struct nv_pmu_rpc_struct_volt_load rpc;
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int status = 0;
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(void) memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_volt_load));
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PMU_RPC_EXECUTE(status, pmu, VOLT, LOAD, &rpc, 0);
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if (status != 0) {
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nvgpu_err(g, "Failed to execute RPC status=0x%x",
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status);
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}
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return status;
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}
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int nvgpu_volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv, u32 sram_voltage_uv)
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{
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return volt_set_voltage(g,
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logic_voltage_uv, sram_voltage_uv);
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}
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int nvgpu_volt_get_voltage(struct gk20a *g, u32 volt_domain, u32 *voltage_uv)
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{
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return volt_rail_get_voltage(g,
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(u8)volt_domain, voltage_uv);
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}
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