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1701a267bc
Create ramfc under common/fifo Created the following HAL: - ramfc.setup - ramfc.commit_userd Moved setup code to ramfc HAL: - vgpu_channel_setup_ramfc - gk20a_fifo_setup_ramfc - channel_gp10b_setup_ramfc - channel_gv11b_setup_ramfc - channel_tu104_setup_ramfc Renamed as: - <chip>_ramfc_setup Moved commit userd code to ramfc HAL: - gk20a_fifo_commit_userd - channel_gp10b_commit_userd Renamed as: - <chip>_ramfc_commit_userd Jira NVGPU-1750 Change-Id: Ieb1bd2866fd77601edd218f879ababf4f90db54a Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2069947 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
53 lines
1.9 KiB
C
53 lines
1.9 KiB
C
/*
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* Virtualized GPU Channel RAMFC
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*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/vgpu/vgpu_ivc.h>
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#include <nvgpu/vgpu/vgpu.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/channel.h>
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#include "ramfc_vgpu.h"
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int vgpu_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
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u32 gpfifo_entries, u64 pbdma_acquire_timeout, u32 flags)
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{
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struct tegra_vgpu_cmd_msg msg;
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struct tegra_vgpu_ramfc_params *p = &msg.params.ramfc;
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int err;
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struct gk20a *g = ch->g;
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nvgpu_log_fn(g, " ");
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msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SETUP_RAMFC;
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msg.handle = vgpu_get_handle(ch->g);
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p->handle = ch->virt_ctx;
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p->gpfifo_va = gpfifo_base;
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p->num_entries = gpfifo_entries;
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p->userd_addr = ch->userd_iova;
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p->iova = 0;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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return (err || msg.ret) ? -ENOMEM : 0;
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}
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