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On gp10b, ramfc contains information related to syncpoint protection, which restricts the syncpoint increment operation to a safe set of syncpoints. This information must be updated when a syncpoint is assigned to a channel. Added the following ramfc HALs - ramfc.get_syncpt - ramfc.set_syncpt And replaced - fifo.resetup_ramfc With - channel.set_syncpt Use new ramfc HALs, move resetup_ramfc implementation from fifo to common channel code: - nvgpu_channel_set_syncpt NVGPU-1750 Change-Id: I036a0b7b2d9fd6ccd9f30094ae33e6c38a96e0cc Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2075938 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
43 lines
1.7 KiB
C
43 lines
1.7 KiB
C
/*
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* GP10B Fifo
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*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef FIFO_GP10B_H
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#define FIFO_GP10B_H
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struct gpu_ops;
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struct channel_gk20a;
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struct fifo_gk20a;
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struct mmu_fault_info;
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void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
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u32 *inst_id, u32 *pri_base, u32 *fault_id);
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void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f);
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void gp10b_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id,
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struct mmu_fault_info *mmfault);
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void gp10b_fifo_get_mmu_fault_desc(struct mmu_fault_info *mmfault);
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void gp10b_fifo_get_mmu_fault_client_desc(struct mmu_fault_info *mmfault);
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int gp10b_fifo_init_ce_engine_info(struct fifo_gk20a *f);
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#endif
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