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b8ceeae21e
Moved enable/disable HALs from fifo to tsg: - tsg.enable - tsg.disable gk20a_tsg_enable and gv11b_tsg_enable are moved to HAL, since they are chip specific, even though they do not directly access chip registers. Removed vgpu_gv11b_tsg_enable as it was identical to gv11b_tsg_enable. Changed gv11b_fifo_locked_abort_runlist_active_tsgs and gv11b_fifo_teardown_ch_tsg to use tsg.enable HAL instead of calling directly gk20a_disable_tsg HAL implementation. Jira NVGPU-2979 Change-Id: I721650c64dcf8cd158652e362292af45df43819f Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2083156 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
68 lines
2.2 KiB
C
68 lines
2.2 KiB
C
/*
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* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/log.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/tsg.h>
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#include <nvgpu/gk20a.h>
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#include "hal/fifo/tsg_gk20a.h"
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void gk20a_tsg_enable(struct tsg_gk20a *tsg)
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{
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struct gk20a *g = tsg->g;
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struct channel_gk20a *ch;
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gk20a_tsg_disable_sched(g, tsg);
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/*
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* Due to h/w bug that exists in Maxwell and Pascal,
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* we first need to enable all channels with NEXT and CTX_RELOAD set,
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* and then rest of the channels should be enabled
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*/
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nvgpu_rwsem_down_read(&tsg->ch_list_lock);
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nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) {
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struct nvgpu_channel_hw_state hw_state;
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g->ops.channel.read_state(g, ch, &hw_state);
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if (hw_state.next || hw_state.ctx_reload) {
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g->ops.channel.enable(ch);
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}
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}
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nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) {
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struct nvgpu_channel_hw_state hw_state;
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g->ops.channel.read_state(g, ch, &hw_state);
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if (hw_state.next || hw_state.ctx_reload) {
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continue;
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}
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g->ops.channel.enable(ch);
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}
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nvgpu_rwsem_up_read(&tsg->ch_list_lock);
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gk20a_tsg_enable_sched(g, tsg);
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}
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