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1ad54446da
Add NVGPU_GRAPHICS flag to support the nvgpu_gr_config_init_map_tiles and map_tiles related functions and variables. Use only when this flag is defined. Jira NVGPU-3583 Change-Id: Ib31a7445bcc573a127d1902bc19fc2aae9548d0f Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2130616 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
75 lines
2.0 KiB
C
75 lines
2.0 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GR_CONFIG_PRIV_H
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#define NVGPU_GR_CONFIG_PRIV_H
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#include <nvgpu/types.h>
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#define GK20A_GR_MAX_PES_PER_GPC 3U
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struct gk20a;
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struct nvgpu_sm_info {
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u32 gpc_index;
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u32 tpc_index;
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u32 sm_index;
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u32 global_tpc_index;
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};
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struct nvgpu_gr_config {
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struct gk20a *g;
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u32 max_gpc_count;
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u32 max_tpc_per_gpc_count;
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u32 max_tpc_count;
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u32 gpc_count;
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u32 tpc_count;
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u32 ppc_count;
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u32 pe_count_per_gpc;
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u32 sm_count_per_tpc;
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u32 *gpc_ppc_count;
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u32 *gpc_tpc_count;
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u32 *pes_tpc_count[GK20A_GR_MAX_PES_PER_GPC];
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u32 gpc_mask;
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u32 *gpc_tpc_mask;
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u32 *pes_tpc_mask[GK20A_GR_MAX_PES_PER_GPC];
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u32 *gpc_skip_mask;
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#ifdef NVGPU_GRAPHICS
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u32 max_zcull_per_gpc_count;
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u32 zcb_count;
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u32 *gpc_zcb_count;
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u8 *map_tiles;
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u32 map_tile_count;
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u32 map_row_offset;
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#endif
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u32 no_of_sm;
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struct nvgpu_sm_info *sm_to_cluster;
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};
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#endif /* NVGPU_GR_CONFIG_PRIV_H */
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