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c5f5eb896c
Add NVGPU_DEBUGGER flag for common.gr.hwpm_map and common.hal.gr.hwpm_map units Jira NVGPU-3505 Change-Id: I5c9b6f98c7a8f536f5a8492febaa6140ef2adb6f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2130147 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
109 lines
2.7 KiB
C
109 lines
2.7 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/types.h>
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#include <nvgpu/gr/gr_utils.h>
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#include <nvgpu/gr/config.h>
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#include "gr_priv.h"
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struct nvgpu_gr_falcon *nvgpu_gr_get_falcon_ptr(struct gk20a *g)
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{
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return g->gr->falcon;
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}
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void nvgpu_gr_reset_falcon_ptr(struct gk20a *g)
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{
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g->gr->falcon = NULL;
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}
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struct nvgpu_gr_obj_ctx_golden_image *nvgpu_gr_get_golden_image_ptr(
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struct gk20a *g)
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{
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return g->gr->golden_image;
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}
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void nvgpu_gr_reset_golden_image_ptr(struct gk20a *g)
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{
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g->gr->golden_image = NULL;
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}
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#ifdef NVGPU_GRAPHICS
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struct nvgpu_gr_zcull *nvgpu_gr_get_zcull_ptr(struct gk20a *g)
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{
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return g->gr->zcull;
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}
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struct nvgpu_gr_zbc *nvgpu_gr_get_zbc_ptr(struct gk20a *g)
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{
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return g->gr->zbc;
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}
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#endif
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struct nvgpu_gr_config *nvgpu_gr_get_config_ptr(struct gk20a *g)
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{
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return g->gr->config;
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}
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#ifdef NVGPU_DEBUGGER
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struct nvgpu_gr_hwpm_map *nvgpu_gr_get_hwpm_map_ptr(struct gk20a *g)
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{
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return g->gr->hwpm_map;
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}
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#endif
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struct nvgpu_gr_intr *nvgpu_gr_get_intr_ptr(struct gk20a *g)
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{
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return g->gr->intr;
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}
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#ifdef CONFIG_GK20A_CTXSW_TRACE
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struct nvgpu_gr_global_ctx_buffer_desc *nvgpu_gr_get_global_ctx_buffer_ptr(
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struct gk20a *g)
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{
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return g->gr->global_ctx_buffer;
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}
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#endif
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u32 nvgpu_gr_get_override_ecc_val(struct gk20a *g)
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{
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return g->gr->fecs_feature_override_ecc_val;
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}
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void nvgpu_gr_override_ecc_val(struct gk20a *g, u32 ecc_val)
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{
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g->gr->fecs_feature_override_ecc_val = ecc_val;
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}
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u32 nvgpu_gr_get_cilp_preempt_pending_chid(struct gk20a *g)
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{
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return g->gr->cilp_preempt_pending_chid;
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}
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void nvgpu_gr_clear_cilp_preempt_pending_chid(struct gk20a *g)
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{
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g->gr->cilp_preempt_pending_chid =
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NVGPU_INVALID_CHANNEL_ID;
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}
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