mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-24 02:22:34 +03:00
c62bdb94ba
- Add a sysfs node "golden_img_status" to show
if golden_image size and ptr are already initialized
or not.
- This node helps to know golden image status before
attempting to modify gpc/tpc/fbp masks.
Bug 3960290
Change-Id: I3c3de69b369bcaf2f0127e897d06e21cb8e2d68e
Signed-off-by: Divya <dsinghatwari@nvidia.com>
(cherry picked from commit c728f09c18)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2864095
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
140 lines
4.3 KiB
C
140 lines
4.3 KiB
C
/*
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* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GR_UTILS_H
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#define NVGPU_GR_UTILS_H
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#include <nvgpu/types.h>
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#include <nvgpu/static_analysis.h>
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/**
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* @file
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*
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* common.gr.utils unit interface
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*/
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struct gk20a;
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struct nvgpu_gr;
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struct nvgpu_gr_falcon;
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struct nvgpu_gr_config;
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struct nvgpu_gr_intr;
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#ifdef CONFIG_NVGPU_DEBUGGER
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struct nvgpu_gr_obj_ctx_golden_image;
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#endif
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#ifdef CONFIG_NVGPU_GRAPHICS
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struct nvgpu_gr_zbc;
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struct nvgpu_gr_zcull;
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#endif
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#ifdef CONFIG_NVGPU_DEBUGGER
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struct nvgpu_gr_hwpm_map;
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#endif
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#ifdef CONFIG_NVGPU_FECS_TRACE
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struct nvgpu_gr_global_ctx_buffer_desc;
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#endif
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/**
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* @brief Compute checksum.
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*
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* @param a [in] First unsigned integer.
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* @param b [in] Second unsigned integer.
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*
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* This function will calculate checksum of two unsigned integers and
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* return the result. This function is typically needed to calculate
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* checksum of falcon ucode boot binary.
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*
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* @return Checksum of two unsigned integers.
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*/
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u32 nvgpu_gr_checksum_u32(u32 a, u32 b);
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/**
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* @brief Get GR falcon data struct pointer.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns pointer to #nvgpu_gr_falcon structure.
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*
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* @return Pointer to GR falcon data struct.
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*/
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struct nvgpu_gr_falcon *nvgpu_gr_get_falcon_ptr(struct gk20a *g);
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/**
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* @brief Get GR configuration struct pointer.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns pointer to #nvgpu_gr_config structure.
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*
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* @return Pointer to GR configuration struct.
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*/
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struct nvgpu_gr_config *nvgpu_gr_get_config_ptr(struct gk20a *g);
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/**
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* @brief Get GR configuration struct pointer.
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*
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* @param g [in] Pointer to GPU driver struct.
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* @param gr_instance_id [in] Gr instance Id.
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*
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* This function returns pointer to #nvgpu_gr_config structure.
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*
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* @return Pointer to GR configuration struct.
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*/
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struct nvgpu_gr_config *nvgpu_gr_get_gr_instance_config_ptr(struct gk20a *g,
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u32 gr_instance_id);
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/**
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* @brief Get GR interrupt data struct pointer.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns pointer to #nvgpu_gr_intr structure.
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*
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* @return Pointer to GR interrupt data struct.
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*/
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struct nvgpu_gr_intr *nvgpu_gr_get_intr_ptr(struct gk20a *g);
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#ifdef CONFIG_NVGPU_NON_FUSA
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/* gr variables */
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u32 nvgpu_gr_get_override_ecc_val(struct gk20a *g);
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void nvgpu_gr_override_ecc_val(struct nvgpu_gr *gr, u32 ecc_val);
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#endif
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#ifdef CONFIG_NVGPU_GRAPHICS
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struct nvgpu_gr_zcull *nvgpu_gr_get_zcull_ptr(struct gk20a *g);
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struct nvgpu_gr_zbc *nvgpu_gr_get_zbc_ptr(struct gk20a *g);
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#endif
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#ifdef CONFIG_NVGPU_CILP
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u32 nvgpu_gr_get_cilp_preempt_pending_chid(struct gk20a *g);
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void nvgpu_gr_clear_cilp_preempt_pending_chid(struct gk20a *g);
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#endif
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struct nvgpu_gr_obj_ctx_golden_image *nvgpu_gr_get_golden_image_ptr(
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struct gk20a *g);
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bool nvgpu_gr_obj_ctx_golden_img_status(struct gk20a *g);
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#ifdef CONFIG_NVGPU_DEBUGGER
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struct nvgpu_gr_hwpm_map *nvgpu_gr_get_hwpm_map_ptr(struct gk20a *g);
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void nvgpu_gr_reset_falcon_ptr(struct gk20a *g);
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void nvgpu_gr_reset_golden_image_ptr(struct gk20a *g);
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#endif
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#ifdef CONFIG_NVGPU_FECS_TRACE
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struct nvgpu_gr_global_ctx_buffer_desc *nvgpu_gr_get_global_ctx_buffer_ptr(
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struct gk20a *g);
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#endif
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#endif /* NVGPU_GR_UTILS_H */
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