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fc27aab523
ga10b can have 2 GPCs and each GPC is clocked with separate gpc clk. Added ga10b specific set_rate/get_rate operations for gpcclks considering GPC floor-sweeping info. Bug 3315239 Change-Id: I4e2156b4e06a1580a60d832e0d3296ed3dc17887 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2617441 Reviewed-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Tejal Kudav <tkudav@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
112 lines
3.0 KiB
C
112 lines
3.0 KiB
C
/*
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* Linux clock support for ga10b
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*
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include "clk.h"
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#include "os_linux.h"
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#include "platform_gk20a.h"
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#include <nvgpu/gk20a.h>
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#include <nvgpu/clk_arb.h>
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#include <nvgpu/gr/gr_utils.h>
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#include <nvgpu/gr/config.h>
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#include <nvgpu/pmu/clk/clk.h>
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/*
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* GA10B clock list:
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* platform->clk[0]- sysclk
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* For GPU Full config:
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* platform->clk[1] - gpc0 clk
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* platform->clk[2] - gpc1 clk
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* platform->clk[3] - fuse clk
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* For GPU GPC Floor-swept config:
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* platform->clk[1] - Active gpc(gpc0/gpc1) clk
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* platform->clk[2] - fuse clk
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*/
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/*
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* GPU clock policy for ga10b:
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* All sys, gpc0 and gpc1 clk are at same rate.
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* So, for clock set_rate, change all clocks for
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* any clock rate change request.
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*/
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/*
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* PWRCLK is used for pmu runs at fixed rate 204MHZ in ga10b
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* PWRCLK is enabled once gpu out of reset. CCF is not
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* supporting any clock set/get calls for PWRCLK. To support
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* legacy code, nvgpu driver only supporting clk_get_rate by
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* returning fixed 204MHz rate
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*/
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#define NVGPU_GA10B_PWRCLK_RATE 204000000UL;
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unsigned long nvgpu_ga10b_linux_clk_get_rate(
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struct gk20a *g, u32 api_domain)
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{
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struct gk20a_platform *platform = gk20a_get_platform(dev_from_gk20a(g));
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unsigned long ret;
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switch (api_domain) {
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case CTRL_CLK_DOMAIN_SYSCLK:
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case CTRL_CLK_DOMAIN_GPCCLK:
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ret = clk_get_rate(platform->clk[0]);
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break;
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case CTRL_CLK_DOMAIN_PWRCLK:
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/* power domain is at fixed clock */
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ret = NVGPU_GA10B_PWRCLK_RATE;
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break;
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default:
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nvgpu_err(g, "unknown clock: %u", api_domain);
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ret = 0;
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break;
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}
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return ret;
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}
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int nvgpu_ga10b_linux_clk_set_rate(struct gk20a *g,
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u32 api_domain, unsigned long rate)
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{
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struct gk20a_platform *platform = gk20a_get_platform(dev_from_gk20a(g));
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struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
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u32 gpc_count = nvgpu_gr_config_get_gpc_count(gr_config);
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int ret;
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switch (api_domain) {
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case CTRL_CLK_DOMAIN_GPCCLK:
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case CTRL_CLK_DOMAIN_SYSCLK:
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ret = clk_set_rate(platform->clk[0], rate);
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ret = clk_set_rate(platform->clk[1], rate);
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/* Set second gpcclk for full-config */
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if (gpc_count == 2U)
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ret = clk_set_rate(platform->clk[2], rate);
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break;
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case CTRL_CLK_DOMAIN_PWRCLK:
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nvgpu_err(g, "unsupported operation: %u", api_domain);
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ret = -EINVAL;
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break;
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default:
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nvgpu_err(g, "unknown clock: %u", api_domain);
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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