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c71e764348
The alloc_insty_block() function in the MM HAL is not a HAL. It does not abstract any HW accesses; instead it just wraps a dma allocation. As such remove it from the HAL and move the single gk20a implementation to common/mm/mm.c as nvgpu_alloc_inst_block(). JIRA NVGPU-2042 Change-Id: I0a586800a11cd230ca43b85f94a35de107f5d1e1 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2109049 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
118 lines
3.8 KiB
C
118 lines
3.8 KiB
C
/*
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* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <trace/events/gk20a.h>
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#include <nvgpu/mm.h>
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#include <nvgpu/vm.h>
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#include <nvgpu/vm_area.h>
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#include <nvgpu/dma.h>
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#include <nvgpu/kmem.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/pramin.h>
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#include <nvgpu/list.h>
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/allocator.h>
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#include <nvgpu/semaphore.h>
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#include <nvgpu/page_allocator.h>
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#include <nvgpu/log.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/log2.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/vidmem.h>
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#include <nvgpu/sizes.h>
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#include <nvgpu/io.h>
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#include <nvgpu/utils.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/pd_cache.h>
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#include <nvgpu/fence.h>
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#include "mm_gk20a.h"
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#include <nvgpu/hw/gk20a/hw_pram_gk20a.h>
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/*
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* GPU mapping life cycle
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* ======================
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*
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* Kernel mappings
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* ---------------
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*
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* Kernel mappings are created through vm.map(..., false):
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*
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* - Mappings to the same allocations are reused and refcounted.
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* - This path does not support deferred unmapping (i.e. kernel must wait for
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* all hw operations on the buffer to complete before unmapping).
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* - References to dmabuf are owned and managed by the (kernel) clients of
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* the gk20a_vm layer.
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*
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*
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* User space mappings
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* -------------------
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*
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* User space mappings are created through as.map_buffer -> vm.map(..., true):
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*
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* - Mappings to the same allocations are reused and refcounted.
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* - This path supports deferred unmapping (i.e. we delay the actual unmapping
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* until all hw operations have completed).
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* - References to dmabuf are owned and managed by the vm_gk20a
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* layer itself. vm.map acquires these refs, and sets
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* mapped_buffer->own_mem_ref to record that we must release the refs when we
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* actually unmap.
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*
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*/
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void gk20a_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm,
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u32 big_page_size)
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{
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struct gk20a *g = gk20a_from_vm(vm);
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u64 pdb_addr = nvgpu_pd_gpu_addr(g, &vm->pdb);
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nvgpu_log_info(g, "inst block phys = 0x%llx, kv = 0x%p",
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nvgpu_inst_block_addr(g, inst_block), inst_block->cpu_va);
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g->ops.ramin.init_pdb(g, inst_block, pdb_addr, vm->pdb.mem);
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g->ops.ramin.set_adr_limit(g, inst_block, vm->va_limit - 1U);
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if ((big_page_size != 0U) && (g->ops.ramin.set_big_page_size != NULL)) {
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g->ops.ramin.set_big_page_size(g, inst_block, big_page_size);
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}
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}
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u32 gk20a_mm_get_iommu_bit(struct gk20a *g)
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{
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return 34;
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}
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u64 gk20a_mm_bar1_map_userd(struct gk20a *g, struct nvgpu_mem *mem, u32 offset)
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{
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struct fifo_gk20a *f = &g->fifo;
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u64 gpu_va = f->userd_gpu_va + offset;
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return nvgpu_gmmu_map_fixed(g->mm.bar1.vm, mem, gpu_va,
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PAGE_SIZE, 0,
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gk20a_mem_flag_none, false,
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mem->aperture);
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}
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