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git://nv-tegra.nvidia.com/linux-nvgpu.git
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3e43f92f21
Mass copy ga10b & ga100 sources from nvgpu-next repo. TOP COMMIT-ID: 98f530e6924c844a1bf46816933a7fe015f3cce1 Jira NVGPU-4771 Change-Id: Ibf7102e9208133f8ef3bd3a98381138d5396d831 Signed-off-by: Sagar Kadamati <skadamati@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2524817 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
93 lines
2.9 KiB
C
93 lines
2.9 KiB
C
/*
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*
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/lock.h>
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#include <nvgpu/cic.h>
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void nvgpu_cic_intr_unit_vectorid_init(struct gk20a *g, u32 unit, u32 *vectorid,
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u32 num_entries)
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{
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unsigned long flags = 0;
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u32 i = 0U;
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struct nvgpu_intr_unit_info *intr_unit_info;
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nvgpu_assert(num_entries <= NVGPU_CIC_INTR_VECTORID_SIZE_MAX);
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nvgpu_log(g, gpu_dbg_intr, "UNIT=%d, nvecs=%d", unit, num_entries);
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intr_unit_info = g->mc.nvgpu_next.intr_unit_info;
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nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
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if (intr_unit_info[unit].valid == false) {
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for (i = 0U; i < num_entries; i++) {
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nvgpu_log(g, gpu_dbg_intr, " vec[%d] = %d", i,
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*(vectorid + i));
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intr_unit_info[unit].vectorid[i] = *(vectorid + i);
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}
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intr_unit_info[unit].vectorid_size = num_entries;
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}
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nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
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}
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bool nvgpu_cic_intr_is_unit_info_valid(struct gk20a *g, u32 unit)
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{
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struct nvgpu_intr_unit_info *intr_unit_info;
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bool info_valid = false;
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if (unit >= NVGPU_CIC_INTR_UNIT_MAX) {
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nvgpu_err(g, "invalid unit(%d)", unit);
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return false;
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}
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intr_unit_info = g->mc.nvgpu_next.intr_unit_info;
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if (intr_unit_info[unit].valid == true) {
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info_valid = true;
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}
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return info_valid;
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}
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bool nvgpu_cic_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree,
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u64 *subtree_mask)
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{
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if (unit >= NVGPU_CIC_INTR_UNIT_MAX) {
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nvgpu_err(g, "invalid unit(%d)", unit);
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return false;
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}
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if (nvgpu_cic_intr_is_unit_info_valid(g, unit) != true) {
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if (g->ops.mc.intr_get_unit_info(g, unit) != true) {
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nvgpu_err(g, "failed to fetch info for unit(%d)", unit);
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return false;
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}
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}
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*subtree = g->mc.nvgpu_next.intr_unit_info[unit].subtree;
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*subtree_mask = g->mc.nvgpu_next.intr_unit_info[unit].subtree_mask;
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nvgpu_log(g, gpu_dbg_intr, "subtree(%d) subtree_mask(%llx)",
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*subtree, *subtree_mask);
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return true;
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}
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