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3e43f92f21
Mass copy ga10b & ga100 sources from nvgpu-next repo. TOP COMMIT-ID: 98f530e6924c844a1bf46816933a7fe015f3cce1 Jira NVGPU-4771 Change-Id: Ibf7102e9208133f8ef3bd3a98381138d5396d831 Signed-off-by: Sagar Kadamati <skadamati@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2524817 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
62 lines
2.1 KiB
C
62 lines
2.1 KiB
C
/*
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* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/utils.h>
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#include <nvgpu/hw_sim.h>
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#include <nvgpu/sim.h>
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#include <nvgpu/string.h>
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static void nvgpu_next_sim_esc_readl(struct gk20a *g,
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const char *path, u32 index, u32 *data)
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{
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int err;
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u32 data_offset;
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sim_write_hdr(g, sim_msg_function_sim_escape_read_v(),
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sim_escape_read_hdr_size());
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*sim_msg_param(g, 0) = index;
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*sim_msg_param(g, 4) = sizeof(u32);
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data_offset = round_up(
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nvgpu_safe_add_u64(strlen(path), 1ULL), sizeof(u32));
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*sim_msg_param(g, 8) = data_offset;
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strcpy((char *)sim_msg_param(g, sim_escape_read_hdr_size()), path);
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err = issue_rpc_and_wait(g);
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if (err == 0) {
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nvgpu_memcpy((u8 *)data, (u8 *)sim_msg_param(g,
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nvgpu_safe_add_u32(data_offset,
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sim_escape_read_hdr_size())),
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sizeof(u32));
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} else {
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*data = 0xffffffff;
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WARN(1, "issue_rpc_and_wait failed err=%d", err);
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}
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}
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void nvgpu_next_init_sim_support(struct gk20a *g)
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{
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if (g->sim) {
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g->sim->esc_readl = nvgpu_next_sim_esc_readl;
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}
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}
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