mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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d0a1f30e66
Add new API nvgpu_get_gpu_instance_id_from_cdev() that returns GPU instance id from nvgpu_cdev pointer. Store cdev pointer in channel private data channel_priv and ctrl node private data gk20a_ctrl_priv. Update below functions to pass cdev pointer : __gk20a_channel_open() gk20a_channel_open_ioctl() In gk20a_channel_ioctl(), extract gpu instance id using cdev pointer stored in channel_priv and new API nvgpu_get_gpu_instance_id_from_cdev(). Extract GR instance id using nvgpu_grmgr_get_gr_instance_id() Invoke context creation API inside nvgpu_gr_exec_with_err_for_instance() so that context is created with correct GR instance id. Jira NVGPU-5648 Change-Id: I5a4e79165e021b56181d08105b2185306a19703b Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2435465 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Lakshmanan M <lm@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
62 lines
2.1 KiB
C
62 lines
2.1 KiB
C
/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __NVGPU_IOCTL_CHANNEL_H__
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#define __NVGPU_IOCTL_CHANNEL_H__
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#include <linux/fs.h>
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#include <nvgpu/cyclestats_snapshot.h>
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struct inode;
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struct file;
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struct gk20a;
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struct nvgpu_channel_open_args;
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struct nvgpu_channel;
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struct nvgpu_cdev;
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struct gk20a_cs_snapshot_client_linux {
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struct gk20a_cs_snapshot_client cs_client;
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u32 dmabuf_fd;
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struct dma_buf *dma_handler;
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};
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struct nvgpu_channel *nvgpu_channel_get_from_file(int fd);
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int gk20a_channel_open(struct inode *inode, struct file *filp);
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int gk20a_channel_release(struct inode *inode, struct file *filp);
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long gk20a_channel_ioctl(struct file *filp,
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unsigned int cmd, unsigned long arg);
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int gk20a_channel_open_ioctl(struct gk20a *g, struct nvgpu_cdev *cdev,
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struct nvgpu_channel_open_args *args);
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int gk20a_channel_cycle_stats(struct nvgpu_channel *ch, int dmabuf_fd);
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void gk20a_channel_free_cycle_stats_buffer(struct nvgpu_channel *ch);
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int gk20a_attach_cycle_stats_snapshot(struct nvgpu_channel *ch,
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u32 dmabuf_fd,
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u32 perfmon_id_count,
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u32 *perfmon_id_start);
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int gk20a_flush_cycle_stats_snapshot(struct nvgpu_channel *ch);
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int gk20a_channel_free_cycle_stats_snapshot(struct nvgpu_channel *ch);
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extern const struct file_operations gk20a_channel_ops;
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u32 nvgpu_get_common_runlist_level(u32 level);
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u32 nvgpu_get_ioctl_graphics_preempt_mode_flags(u32 graphics_preempt_mode_flags);
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u32 nvgpu_get_ioctl_compute_preempt_mode_flags(u32 compute_preempt_mode_flags);
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u32 nvgpu_get_ioctl_graphics_preempt_mode(u32 graphics_preempt_mode);
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u32 nvgpu_get_ioctl_compute_preempt_mode(u32 compute_preempt_mode);
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#endif
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