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Implement nvgpu plumbing to allow reporting ECC errors(corrected and uncorrected) to a L1SS service(if one exists). This patch includes the following 1) Added code that submits ECC error reports via the Interrupt context directly to a L1SS service in linux OS. 2) Added support for enabling/disabling the error reports via L1SS's registration/deregistration API. Nvgpu simply invokes an empty function until the registration is successful. 3) Added Spinlock to correctly handle concurrency for accessing the correct Ops for submitting requests. 4) Adds error reporting for a subset of interrupts that can be verified via external ECC injection logic. A subsequent patch will add the API for rest of the interrupts. 5) In case of critical(uncorrected errors), change nvgpu's state to quiesce state. Jira L4T-1187 Bug 200700400 Change-Id: Id31f70531fba355e94e72c4f9762593e7667a11c Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2530411 Tested-by: Bibek Basu <bbasu@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
193 lines
4.3 KiB
C
193 lines
4.3 KiB
C
/*
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef NVGPU_OS_LINUX_H
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#define NVGPU_OS_LINUX_H
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#include <linux/cdev.h>
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#include <linux/iommu.h>
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#include <linux/hashtable.h>
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#include <nvgpu/gk20a.h>
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#include "cde.h"
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#include "sched.h"
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#include "ecc_linux.h"
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struct nvgpu_os_linux_ops {
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struct {
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void (*get_program_numbers)(struct gk20a *g,
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u32 block_height_log2,
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u32 shader_parameter,
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int *hprog, int *vprog);
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bool (*need_scatter_buffer)(struct gk20a *g);
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int (*populate_scatter_buffer)(struct gk20a *g,
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struct sg_table *sgt,
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size_t surface_size,
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void *scatter_buffer_ptr,
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size_t scatter_buffer_size);
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} cde;
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struct {
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int (*init_debugfs)(struct gk20a *g);
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} clk;
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struct {
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int (*init_debugfs)(struct gk20a *g);
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} therm;
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struct {
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int (*init_debugfs)(struct gk20a *g);
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} fecs_trace;
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};
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struct nvgpu_os_linux {
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struct gk20a g;
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struct device *dev;
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struct {
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struct cdev cdev;
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struct device *node;
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} channel;
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struct {
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struct cdev cdev;
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struct device *node;
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/* see gk20a_ctrl_priv */
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struct nvgpu_list_node privs;
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/* guards modifications to the list and its contents */
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struct nvgpu_mutex privs_lock;
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} ctrl;
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struct {
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struct cdev cdev;
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struct device *node;
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} as_dev;
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struct {
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struct cdev cdev;
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struct device *node;
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} dbg;
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struct {
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struct cdev cdev;
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struct device *node;
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} prof;
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struct {
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struct cdev cdev;
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struct device *node;
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} tsg;
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struct {
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struct cdev cdev;
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struct device *node;
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} ctxsw;
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struct {
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struct cdev cdev;
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struct device *node;
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} sched;
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dev_t cdev_region;
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struct devfreq *devfreq;
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struct device_dma_parameters dma_parms;
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atomic_t hw_irq_stall_count;
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atomic_t hw_irq_nonstall_count;
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struct nvgpu_cond sw_irq_stall_last_handled_wq;
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atomic_t sw_irq_stall_last_handled;
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atomic_t nonstall_ops;
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struct nvgpu_cond sw_irq_nonstall_last_handled_wq;
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atomic_t sw_irq_nonstall_last_handled;
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struct work_struct nonstall_fn_work;
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struct workqueue_struct *nonstall_work_queue;
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struct resource *reg_mem;
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void __iomem *regs;
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void __iomem *regs_saved;
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struct resource *bar1_mem;
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void __iomem *bar1;
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void __iomem *bar1_saved;
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void __iomem *usermode_regs;
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void __iomem *usermode_regs_saved;
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u64 regs_bus_addr;
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#ifdef CONFIG_NVGPU_SUPPORT_LINUX_ECC_ERROR_REPORTING
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struct nvgpu_ecc_reporting_linux ecc_reporting_linux;
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#endif
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struct nvgpu_os_linux_ops ops;
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#ifdef CONFIG_DEBUG_FS
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struct dentry *debugfs;
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struct dentry *debugfs_alias;
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struct dentry *debugfs_ltc_enabled;
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struct dentry *debugfs_timeouts_enabled;
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struct dentry *debugfs_gr_idle_timeout_default;
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struct dentry *debugfs_disable_bigpage;
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struct dentry *debugfs_gr_default_attrib_cb_size;
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struct dentry *debugfs_timeslice_low_priority_us;
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struct dentry *debugfs_timeslice_medium_priority_us;
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struct dentry *debugfs_timeslice_high_priority_us;
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struct dentry *debugfs_runlist_interleave;
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struct dentry *debugfs_allocators;
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struct dentry *debugfs_xve;
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struct dentry *debugfs_kmem;
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struct dentry *debugfs_hal;
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struct dentry *debugfs_ltc;
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struct dentry *debugfs_force_preemption_cilp;
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struct dentry *debugfs_force_preemption_gfxp;
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struct dentry *debugfs_dump_ctxsw_stats;
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#endif
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DECLARE_HASHTABLE(ecc_sysfs_stats_htable, 5);
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struct dev_ext_attribute *ecc_attrs;
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struct gk20a_cde_app cde_app;
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struct rw_semaphore busy_lock;
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bool init_done;
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};
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static inline struct nvgpu_os_linux *nvgpu_os_linux_from_gk20a(struct gk20a *g)
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{
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return container_of(g, struct nvgpu_os_linux, g);
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}
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static inline struct device *dev_from_gk20a(struct gk20a *g)
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{
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return nvgpu_os_linux_from_gk20a(g)->dev;
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}
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#define INTERFACE_NAME "nvhost%s-gpu"
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#define totalram_size_in_mb (totalram_pages >> (10 - (PAGE_SHIFT - 10)))
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#endif
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