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cb63f7db2f
-Moved NVGPU-ACR interfaces to separate header file from ACR blob/bootstrap header files. -Separation needed for NVGPU-ACR interface specification doxygen. JIRA NVGPU-4152 Change-Id: Ia502380e62f53e0372549544e31ffff150e05017 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2219038 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
226 lines
7.0 KiB
C
226 lines
7.0 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_ACR_INTERFACE_H
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#define NVGPU_ACR_INTERFACE_H
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/* BLOB construct interface */
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/*
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* Light Secure WPR Content Alignments
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*/
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#define LSF_WPR_HEADER_ALIGNMENT (256U)
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#define LSF_SUB_WPR_HEADER_ALIGNMENT (256U)
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#define LSF_LSB_HEADER_ALIGNMENT (256U)
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#define LSF_BL_DATA_ALIGNMENT (256U)
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#define LSF_BL_DATA_SIZE_ALIGNMENT (256U)
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#define LSF_BL_CODE_SIZE_ALIGNMENT (256U)
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#define LSF_DATA_SIZE_ALIGNMENT (256U)
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#define LSF_CODE_SIZE_ALIGNMENT (256U)
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#define LSF_UCODE_DATA_ALIGNMENT 4096U
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/*
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* Maximum WPR Header size
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*/
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#define LSF_WPR_HEADERS_TOTAL_SIZE_MAX \
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(ALIGN_UP(((u32)sizeof(struct lsf_wpr_header) * FALCON_ID_END), \
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LSF_WPR_HEADER_ALIGNMENT))
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#define LSF_LSB_HEADER_TOTAL_SIZE_MAX (\
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ALIGN_UP(sizeof(struct lsf_lsb_header), LSF_LSB_HEADER_ALIGNMENT))
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#ifdef CONFIG_NVGPU_DGPU
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/* Maximum SUB WPR header size */
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#define LSF_SUB_WPR_HEADERS_TOTAL_SIZE_MAX (ALIGN_UP( \
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(sizeof(struct lsf_shared_sub_wpr_header) * \
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LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX), \
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LSF_SUB_WPR_HEADER_ALIGNMENT))
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/* MMU excepts sub_wpr sizes in units of 4K */
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#define SUB_WPR_SIZE_ALIGNMENT (4096U)
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/* Defined for 1MB alignment */
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#define SHIFT_4KB (12U)
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/* shared sub_wpr use case IDs */
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enum {
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LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_FRTS_VBIOS_TABLES = 1,
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LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA = 2
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};
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#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX \
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LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA
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#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_INVALID (0xFFFFFFFFU)
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#define MAX_SUPPORTED_SHARED_SUB_WPR_USE_CASES \
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LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX
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/* Static sizes of shared subWPRs */
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/* Minimum granularity supported is 4K */
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/* 1MB in 4K */
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#define LSF_SHARED_DATA_SUB_WPR_FRTS_VBIOS_TABLES_SIZE_IN_4K (0x100U)
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/* 4K */
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#define LSF_SHARED_DATA_SUB_WPR_PLAYREADY_SHARED_DATA_SIZE_IN_4K (0x1U)
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#endif
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/*Light Secure Bootstrap header related defines*/
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#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0U
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#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE BIT32(0)
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#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0U
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#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE BIT32(2)
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#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE BIT32(3)
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#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE 0U
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/*
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* Image Status Defines
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*/
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#define LSF_IMAGE_STATUS_NONE (0U)
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#define LSF_IMAGE_STATUS_COPY (1U)
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#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED (2U)
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#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED (3U)
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#define LSF_IMAGE_STATUS_VALIDATION_DONE (4U)
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#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED (5U)
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#define LSF_IMAGE_STATUS_BOOTSTRAP_READY (6U)
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struct lsf_wpr_header {
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u32 falcon_id;
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u32 lsb_offset;
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u32 bootstrap_owner;
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u32 lazy_bootstrap;
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u32 bin_version;
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u32 status;
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};
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struct lsf_ucode_desc {
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u8 prd_keys[2][16];
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u8 dbg_keys[2][16];
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u32 b_prd_present;
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u32 b_dbg_present;
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u32 falcon_id;
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u32 bsupports_versioning;
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u32 version;
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u32 dep_map_count;
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u8 dep_map[FALCON_ID_END * 2 * 4];
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u8 kdf[16];
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};
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struct lsf_lsb_header {
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struct lsf_ucode_desc signature;
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u32 ucode_off;
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u32 ucode_size;
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u32 data_size;
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u32 bl_code_size;
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u32 bl_imem_off;
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u32 bl_data_off;
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u32 bl_data_size;
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u32 app_code_off;
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u32 app_code_size;
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u32 app_data_off;
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u32 app_data_size;
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u32 flags;
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};
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struct flcn_bl_dmem_desc {
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u32 reserved[4]; /*Should be the first element..*/
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u32 signature[4]; /*Should be the first element..*/
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u32 ctx_dma;
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struct falc_u64 code_dma_base;
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u32 non_sec_code_off;
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u32 non_sec_code_size;
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u32 sec_code_off;
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u32 sec_code_size;
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u32 code_entry_point;
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struct falc_u64 data_dma_base;
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u32 data_size;
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u32 argc;
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u32 argv;
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};
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/* ACR HS ucode interface */
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/*
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* Supporting maximum of 2 regions.
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* This is needed to pre-allocate space in DMEM
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*/
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#define NVGPU_FLCN_ACR_MAX_REGIONS (2U)
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#define LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE (0x200U)
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/*
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* start_addr - Starting address of region
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* end_addr - Ending address of region
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* region_id - Region ID
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* read_mask - Read Mask
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* write_mask - WriteMask
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* client_mask - Bit map of all clients currently using this region
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*/
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struct flcn_acr_region_prop {
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u32 start_addr;
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u32 end_addr;
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u32 region_id;
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u32 read_mask;
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u32 write_mask;
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u32 client_mask;
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u32 shadowmMem_startaddress;
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};
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/*
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* no_regions - Number of regions used.
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* region_props - Region properties
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*/
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struct flcn_acr_regions {
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u32 no_regions;
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struct flcn_acr_region_prop region_props[NVGPU_FLCN_ACR_MAX_REGIONS];
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};
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/*
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* reserved_dmem-When the bootstrap owner has done bootstrapping other falcons,
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* and need to switch into LS mode, it needs to have its own
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* actual DMEM image copied into DMEM as part of LS setup. If
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* ACR desc is at location 0, it will definitely get overwritten
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* causing data corruption. Hence we are reserving 0x200 bytes
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* to give room for any loading data. NOTE: This has to be the
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* first member always
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* signature - Signature of ACR ucode.
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* wpr_region_id - Region ID holding the WPR header and its details
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* wpr_offset - Offset from the WPR region holding the wpr header
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* regions - Region descriptors
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* nonwpr_ucode_blob_start -stores non-WPR start where kernel stores ucode blob
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* nonwpr_ucode_blob_end -stores non-WPR end where kernel stores ucode blob
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*/
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struct flcn_acr_desc {
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union {
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u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)];
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} ucode_reserved_space;
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u32 signatures[4];
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/*Always 1st*/
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u32 wpr_region_id;
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u32 wpr_offset;
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u32 mmu_mem_range;
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struct flcn_acr_regions regions;
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u32 nonwpr_ucode_blob_size;
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u64 nonwpr_ucode_blob_start;
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u32 dummy[4]; /* ACR_BSI_VPR_DESC */
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};
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#endif /* NVGPU_ACR_INTERFACE_H */
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