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3e43f92f21
Mass copy ga10b & ga100 sources from nvgpu-next repo. TOP COMMIT-ID: 98f530e6924c844a1bf46816933a7fe015f3cce1 Jira NVGPU-4771 Change-Id: Ibf7102e9208133f8ef3bd3a98381138d5396d831 Signed-off-by: Sagar Kadamati <skadamati@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2524817 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
101 lines
3.7 KiB
C
101 lines
3.7 KiB
C
/*
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* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/types.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/io.h>
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#include <nvgpu/runlist.h>
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#include "usermode_ga10b.h"
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#include "hal/fifo/fifo_utils_ga10b.h"
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#include <nvgpu/hw/ga10b/hw_runlist_ga10b.h>
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#define GFID_INSTANCE_0 0U
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/*
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* nvgpu_fifo.max_runlists:
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* - Maximum runlists supported by hardware.
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* nvgpu_fifo.num_runlists:
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* - Number of valid runlists detected during device info parsing and
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* connected to a valid engine.
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* nvgpu_fifo.runlists[]:
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* - This is an array of pointers to nvgpu_runlist_info structure.
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* - This is indexed by hardware runlist_id from 0 to max_runlists.
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* nvgpu_fifo.active_runlists[]:
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* - This is an array of nvgpu_runlist_info structure.
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* - This is indexed by software [consecutive] runlist_ids from 0 to
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* num_runlists.
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*
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* runlists[] pointers at valid runlist_id indices contain valid
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* nvgpu_runlist structures. runlist[] pointers at invalid runlist_id
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* indexes point to NULL. This is explained in the example below.
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*
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* for example: max_runlists = 10, num_runlists = 4
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* say valid runlist_ids are = {0, 2, 3, 7}
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*
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* runlist_info active_runlists
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* 0 ________________ 0 ___________________________
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* |________________|----------------->|___________________________|
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* |________________| |------------->|___________________________|
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* |________________|---| |---------->|___________________________|
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* |________________|------| |------->|___________________________|
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* |________________| | num_runlists
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* |________________| |
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* |________________| |
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* |________________|---------|
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* |________________|
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* |________________|
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* max_runlists
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*
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*/
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void ga10b_usermode_setup_hw(struct gk20a *g)
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{
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struct nvgpu_runlist *runlist = NULL;
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u32 reg_val = 0U;
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u32 i = 0U;
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u32 max_runlist = g->ops.runlist.count_max(g);
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for (i = 0U; i < max_runlist; i++) {
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runlist = g->fifo.runlists[i];
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if (runlist == NULL) {
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continue;
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}
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/*
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* At this moment, we are not supporting multiple GFIDs.
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* Only GFID 0 is supported and passed to
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* runlist_virtual_channel_cfg_r()
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*/
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reg_val = nvgpu_runlist_readl(g, runlist,
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runlist_virtual_channel_cfg_r(GFID_INSTANCE_0));
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reg_val |= runlist_virtual_channel_cfg_mask_hw_mask_hw_init_f();
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reg_val |= runlist_virtual_channel_cfg_pending_enable_true_f();
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nvgpu_runlist_writel(g, runlist,
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runlist_virtual_channel_cfg_r(GFID_INSTANCE_0),
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reg_val);
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}
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}
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