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3d9c67a0e7
Most of the Orin chip specific code is compiled out of safety build with CONFIG_NVGPU_NON_FUSA and CONFIG_NVGPU_HAL_NON_FUSA. Remove the config protection from Orin/GA10B specific code. Currently all code is enabled. Code not required in safety will be compiled out later in separate activity. Other noteworthy changes in this patch related to safety build: - In ga10b_ce_request_idle(), add a log print to dump num_pce so that compiler does not complain about unused variable num_pce. - In ga10b_fifo_ctxsw_timeout_isr(), protect variables active_eng_id and recover under CONFIG_NVGPU_KERNEL_MODE_SUBMIT to fix compilation errors of unused variables. - Compile out HAL gops.pbdma.force_ce_split() from safety since this HAL is GA100 specific and not required for GA10B. - Compile out gr_ga100_process_context_buffer_priv_segment() with CONFIG_NVGPU_DEBUGGER. - Compile out VAB support with CONFIG_NVGPU_HAL_NON_FUSA. - In ga10b_gr_intr_handle_sw_method(), protect left_shift_by_2 variable with appropriate configs to fix unused variable compilation error. - In ga10b_intr_isr_stall_host2soc_3(), compile ELPG function calls with CONFIG_NVGPU_POWER_PG. - In ga10b_pmu_handle_swgen1_irq(), move whole function body under CONFIG_NVGPU_FALCON_DEBUG to fix unused variable compilation errors. - Add below TU104 specific files in safety build since some of the code in those files is required for GA10B. Unnecessary code will be compiled out later on. hal/gr/init/gr_init_tu104.c hal/class/class_tu104.c hal/mc/mc_tu104.c hal/fifo/usermode_tu104.c hal/gr/falcon/gr_falcon_tu104.c - Compile out GA10B specific debugger/profiler related files from safety build. - Disable CONFIG_NVGPU_FALCON_DEBUG from safety debug build temporarily to work around compilation errors seen with keeping this config enabled. Config will be re-enabled in safety debug build later. Jira NVGPU-7276 Change-Id: I35f2489830ac083d52504ca411c3f1d96e72fc48 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2627048 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
424 lines
16 KiB
C
424 lines
16 KiB
C
/*
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* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_ENGINE_H
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#define NVGPU_ENGINE_H
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/**
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* @file
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*
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* Abstract interface for engine related functionality.
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*/
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#include <nvgpu/types.h>
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struct gk20a;
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struct nvgpu_device;
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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#define ENGINE_PBDMA_INSTANCE0 0U
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int nvgpu_engine_init_one_dev_extra(struct gk20a *g,
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const struct nvgpu_device *dev);
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/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
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/**
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* Invalid engine id value.
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*/
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#define NVGPU_INVALID_ENG_ID (~U32(0U))
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struct gk20a;
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struct nvgpu_fifo;
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struct nvgpu_device;
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/**
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* Engine enum types used for s/w purpose. These enum values are
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* different as compared to engine enum types defined by h/w.
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* Refer device.h header file.
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*/
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enum nvgpu_fifo_engine {
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/** GR engine enum */
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NVGPU_ENGINE_GR = 0U,
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/** GR CE engine enum */
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NVGPU_ENGINE_GRCE = 1U,
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/** Async CE engine enum */
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NVGPU_ENGINE_ASYNC_CE = 2U,
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/** Invalid engine enum */
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NVGPU_ENGINE_INVAL = 3U,
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};
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/**
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* @brief Get s/w defined engine enum type for engine enum type defined by h/w.
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* See device.h for engine enum types defined by h/w.
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*
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* @param g [in] The GPU driver struct.
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* @param dev [in] Device to check.
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*
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* This is used to map engine enum type defined by h/w to engine enum type
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* defined by s/w.
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*
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* @return S/w defined valid engine enum type < #NVGPU_ENGINE_INVAL.
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* @retval #NVGPU_ENGINE_INVAL in case h/w #engine_type
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* does not support gr (graphics) and ce (copy engine) engine enum
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* types or if #engine_type does not match with h/w defined engine enum
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* types for gr and/or ce engines.
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*/
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enum nvgpu_fifo_engine nvgpu_engine_enum_from_dev(struct gk20a *g,
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const struct nvgpu_device *dev);
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/**
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* @brief Get pointer to #nvgpu_device for the h/w engine id.
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*
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* @param g [in] The GPU driver struct.
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* @param engine_id [in] Active (h/w) Engine id.
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*
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* If #engine_id is one of the supported h/w engine ids, get pointer to
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* #nvgpu_engine_info from an array of structures that is indexed by h/w
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* engine id.
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*
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* @return Pointer to #nvgpu_device.
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* @retval NULL if #g is NULL.
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* @retval NULL if engine_id is not less than max supported number of engines
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* i.e. #nvgpu_fifo.max_engines or if #engine_id does not match with
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* any engine id supported by h/w or number of available engines
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* i.e. #nvgpu_fifo.num_engines is 0.
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*/
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const struct nvgpu_device *nvgpu_engine_get_active_eng_info(
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struct gk20a *g, u32 engine_id);
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/**
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* @brief Check if engine id is one of the supported h/w engine ids.
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*
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* @param g [in] The GPU driver struct.
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* @param engine_id [in] Engine id.
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*
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* Check if #engine_id is one of the supported active engine ids.
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*
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* @return True if #engine_id is valid.
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* @retval False if engine_id is not less than maximum number of supported
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* engines on the chip i.e. #nvgpu_fifo.max_engines or if engine id
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* does not match with any of the engine ids supported by h/w.
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*/
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bool nvgpu_engine_check_valid_id(struct gk20a *g, u32 engine_id);
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/**
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* @brief Get h/w engine id based on engine's instance identification number
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* #NVGPU_ENGINE_GR engine enum type.
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*
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* @param g [in] The GPU driver struct.
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* @param inst_id [in] Engine's instance identification number.
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*
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* @return H/W engine id for #NVGPU_ENGINE_GR engine enum type.
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* @retval #NVGPU_INVALID_ENG_ID if #NVGPU_ENGINE_GR engine enum type could not
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* be found in the set of available h/w engine ids.
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*/
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u32 nvgpu_engine_get_gr_id_for_inst(struct gk20a *g, u32 inst_id);
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/**
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* @brief Get instance count and first available h/w engine id for
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* #NVGPU_ENGINE_GR engine enum type.
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*
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* @param g [in] The GPU driver struct.
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*
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* Call #nvgpu_engine_get_ids to get first available #NVGPU_ENGINE_GR
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* engine enum type.
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*
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* @return First available h/w engine id for #NVGPU_ENGINE_GR engine enum type.
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* @retval #NVGPU_INVALID_ENG_ID if #NVGPU_ENGINE_GR engine enum type could not
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* be found in the set of available h/w engine ids.
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*/
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u32 nvgpu_engine_get_gr_id(struct gk20a *g);
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/**
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* @brief Get intr mask for the GR engine supported by the chip.
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*
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* @param g[in] The GPU driver struct.
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*
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* Return bitmask of each GR engine's interrupt bit.
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*
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* @return Interrupt mask for GR engine.
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*/
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u32 nvgpu_gr_engine_interrupt_mask(struct gk20a *g);
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/**
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* @brief Get intr mask for the CE engines supported by the chip.
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*
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* @param g [in] The GPU driver struct.
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*
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* Query all types of copy engine devices and OR their interrupt bits into
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* a CE interrupt mask.
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*
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* @return 0U if there is no CE support in the system.
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* @return The logical OR of all interrupt bits for all CE devices present.
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*/
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u32 nvgpu_ce_engine_interrupt_mask(struct gk20a *g);
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/**
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* @brief Get intr mask for the device corresponding the provided engine_id.
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*
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* @param g [in] The GPU driver struct.
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* @param engine_id [in] HW engine_id.
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*
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* Return the interrupt mask for the host device corresponding to \a engine_id.
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*
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* @return Intr mask for the #engine_id or 0 if the engine_id does not have a
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* corresponding device.
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*/
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u32 nvgpu_engine_act_interrupt_mask(struct gk20a *g, u32 engine_id);
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/**
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* @brief Allocate and initialize s/w context for engine related info.
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*
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* @param g [in] The GPU driver struct.
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*
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* - Get max number of engines supported on the chip from h/w config register.
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* - Allocate kernel memory area for storing engine info for max number of
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* engines supported on the chip. This allocated area of memory is set to 0
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* and then filled with value read from device info h/w registers.
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* Also this area of memory is indexed by h/w engine id.
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* - Allocate kernel memory area for max number of engines supported on the
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* chip to map s/w defined engine ids starting from 0 to h/w (active) engine
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* id read from device info h/w register. This allocated area of memory is
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* set to 0xff and then filled with engine id read from device info h/w
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* registers. This area of memory is indexed by s/w defined engine id starting
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* from 0.
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* - Initialize engine info related s/w context by calling hal that will read
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* device info h/w registers and also initialize s/w variable
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* #nvgpu_fifo.num_engines that is used to count total number of valid h/w
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* engine ids read from device info h/w registers.
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*
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* @return 0 upon success, < 0 otherwise.
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* @retval -ENOMEM upon failure to allocate memory for engine structure.
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* @retval -EINVAL upon failure to get engine info from device info h/w
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* registers.
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*/
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int nvgpu_engine_setup_sw(struct gk20a *g);
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/**
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* @brief Clean up s/w context for engine related info.
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*
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* @param g [in] The GPU driver struct.
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*
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* - Free up kernel memory area that is used for storing engine info read
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* from device info h/w registers.
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* - Free up kernel memory area to map s/w defined engine ids (starting with 0)
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* to active (h/w) engine ids read from device info h/w register.
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*/
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void nvgpu_engine_cleanup_sw(struct gk20a *g);
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#ifdef CONFIG_NVGPU_FIFO_ENGINE_ACTIVITY
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void nvgpu_engine_enable_activity_all(struct gk20a *g);
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int nvgpu_engine_disable_activity(struct gk20a *g,
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const struct nvgpu_device *dev,
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bool wait_for_idle);
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int nvgpu_engine_disable_activity_all(struct gk20a *g,
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bool wait_for_idle);
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int nvgpu_engine_wait_for_idle(struct gk20a *g);
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#endif
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#ifdef CONFIG_NVGPU_ENGINE_RESET
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/**
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* Called from recovery. This will not be part of the safety build after
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* recovery is not supported in the safety build.
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*/
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void nvgpu_engine_reset(struct gk20a *g, u32 engine_id);
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#endif
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/**
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* @brief Get runlist id for the last available #NVGPU_ENGINE_ASYNC_CE
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* engine enum type.
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*
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* @param g [in] The GPU driver struct.
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*
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* - Call #nvgpu_engine_get_gr_runlist_id to get runlist id for the first
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* available #NVGPU_ENGINE_GR engine type.
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* - Get #nvgpu_engine_info.runlist_id for last available #NVGPU_ENGINE_ASYNC_CE
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* engine enum type.
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* - Get pointer to #nvgpu_engine_info for each of #nvgpu_fifo.num_engines.
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* - Get #nvgpu_engine_info.runlist_id for the #nvgpu_engine_info.engine_enum
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* type matching with #NVGPU_ENGINE_ASYNC_CE.
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*
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* @return #nvgpu_engine_info.runlist_id for the last available
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* #NVGPU_ENGINE_ASYNC_CE engine enum type.
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* @retval Return value of #nvgpu_engine_get_gr_runlist_id if #g is NULL.
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* @retval Return value of #nvgpu_engine_get_gr_runlist_id if
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* #NVGPU_ENGINE_ASYNC_CE engine enum type is not available.
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* @retval Return value of #nvgpu_engine_get_gr_runlist_id if
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* #nvgpu_fifo.num_engines is 0.
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*/
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u32 nvgpu_engine_get_fast_ce_runlist_id(struct gk20a *g);
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/**
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* @brief Get runlist id for the first available #NVGPU_ENGINE_GR engine enum
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* type.
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*
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* @param g [in] The GPU driver struct.
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*
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* - Get h/w engine id for the first available #NVGPU_ENGINE_GR engine enum
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* type.
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* -- Get #nvgpu_engine_info for the first available gr engine id.
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* -- Get #nvgpu_engine_info.runlist_id for first available gr engine id.
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*
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* @return #nvgpu_engine_info.runlist_id for the first available gr engine id.
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* @retval U32_MAX if #NVGPU_ENGINE_GR engine enum type is not available.
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* @retval U32_MAX if pointer to #nvgpu_engine_info for the first available
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* gr h/w engine id is NULL.
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*/
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u32 nvgpu_engine_get_gr_runlist_id(struct gk20a *g);
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/**
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* @brief Check if runlist id corresponds to runlist id of one of the
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* engine ids supported by h/w.
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*
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* @param g [in] The GPU driver struct.
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* @param runlist_id [in] Runlist id.
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*
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* Check if #runlist_id corresponds to runlist id of one of the engine
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* ids supported by h/w by checking #nvgpu_engine_info for each of
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* #nvgpu_fifo.num_engines engines.
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*
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* @return True if #runlist_id is valid.
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* @return False if #nvgpu_engine_info is NULL for all the engine ids starting
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* with 0 upto #nvgpu_fifo.num_engines or #runlist_id did not match with
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* any of the runlist ids of engine ids supported by h/w.
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*/
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bool nvgpu_engine_is_valid_runlist_id(struct gk20a *g, u32 runlist_id);
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/**
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* @brief Get mmu fault id for the engine id.
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*
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* @param g [in] The GPU driver struct.
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* @param engine_id [in] Engine id.
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*
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* Get pointer to #nvgpu_engine_info for the #engine_id. Use this pointer to
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* get mmu fault id for the #engine_id.
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*
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* @return Mmu fault id for #engine_id.
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* @retval Invalid mmu fault id, #NVGPU_INVALID_ENG_ID.
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*/
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u32 nvgpu_engine_id_to_mmu_fault_id(struct gk20a *g, u32 engine_id);
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/**
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* @brief Get engine id from mmu fault id.
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*
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* @param g [in] The GPU driver struct.
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* @param fault_id [in] Mmu fault id.
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*
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* Check if #fault_id corresponds to fault id of one of the active engine
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* ids supported by h/w by checking #nvgpu_engine_info for each of
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* #nvgpu_fifo.num_engines engines.
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*
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* @return Valid engine id corresponding to #fault_id.
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* @retval Invalid engine id, #NVGPU_INVALID_ENG_ID if pointer to
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* #nvgpu_engine_info is NULL for the engine ids starting with
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* 0 upto #nvgpu_fifo.num_engines or
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* #fault_id did not match with any of the fault ids of h/w engine ids.
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*/
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u32 nvgpu_engine_mmu_fault_id_to_engine_id(struct gk20a *g, u32 fault_id);
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/**
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* Called from recovery. This will not be part of the safety build after
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* recovery is not supported in the safety build.
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*/
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u32 nvgpu_engine_get_mask_on_id(struct gk20a *g, u32 id, bool is_tsg);
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/**
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* @brief Read device info h/w registers to get engine info.
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*
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* @param f [in] Pointer to #nvgpu_fifo struct.
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*
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* - Get device info related info for h/w engine enum type,
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* #NVGPU_DEVTYPE_GRAPHICS.
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* - Get PBDMA id serving the runlist id of the h/w engine enum type,
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* #NVGPU_DEVTYPE_GRAPHICS.
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* - Get s/w defined engine enum type for the h/w engine enum type read
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* from device info registers.
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* - Initialize #nvgpu_fifo.engine_info and #nvgpu_fifo.active_engines_list
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* with the data from local device info struct and also initialize s/w
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* variable.
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* #nvgpu_fifo.num_engines that is used to count total number of valid h/w
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* engine ids read from device info h/w registers.
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* - Call function to initialize CE engine info.
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*
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* @return 0 upon success.
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* @retval -EINVAL if call to function to get device info related info for
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* h/w engine enum type, #NVGPU_DEVTYPE_GRAPHICS returned failure.
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* @retval -EINVAL if call to function to get pbdma id for runlist id of
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* h/w engine enum type, #NVGPU_DEVTYPE_GRAPHICS returned failure.
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* @retval Return value of function called to initialize CE engine info.
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*/
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int nvgpu_engine_init_info(struct nvgpu_fifo *f);
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/**
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* Called from recovery handling for architectures before volta. This will
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* not be part of safety build after recovery is not supported in the safety
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* build.
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*/
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void nvgpu_engine_get_id_and_type(struct gk20a *g, u32 engine_id,
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u32 *id, u32 *type);
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/**
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* Called from ctxsw timeout intr handling. This function will not be part
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* of safety build after recovery is not supported in the safety build.
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*/
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u32 nvgpu_engine_find_busy_doing_ctxsw(struct gk20a *g,
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u32 *id_ptr, bool *is_tsg_ptr);
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/**
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* Called from runlist update timeout handling. This function will not be part
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* of safety build after recovery is not supported in safety build.
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*/
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u32 nvgpu_engine_get_runlist_busy_engines(struct gk20a *g, u32 runlist_id);
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#ifdef CONFIG_NVGPU_DEBUGGER
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bool nvgpu_engine_should_defer_reset(struct gk20a *g, u32 engine_id,
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u32 engine_subid, bool fake_fault);
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#endif
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/**
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* @brief Get veid from mmu fault id.
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*
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* @param g [in] The GPU driver struct.
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* @param mmu_fault_id [in] Mmu fault id.
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* @param gr_eng_fault_id [in] GR engine's mmu fault id.
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*
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* Get valid veid by subtracting #gr_eng_fault_id from #mmu_fault_id,
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* if #mmu_fault_id is greater than or equal to #gr_eng_fault_id and less
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* than #gr_eng_fault_id + #nvgpu_fifo.max_subctx_count.
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*
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* @return Veid.
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* @retval Invalid veid, #INVAL_ID.
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*/
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u32 nvgpu_engine_mmu_fault_id_to_veid(struct gk20a *g, u32 mmu_fault_id,
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u32 gr_eng_fault_id);
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/**
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* @brief Get engine id, veid and pbdma id from mmu fault id.
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*
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* @param g [in] The GPU driver struct.
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* @param mmu_fault_id [in] Mmu fault id.
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* @param engine_id [in,out] Pointer to store active engine id.
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* @param veid [in,out] Pointer to store veid.
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* @param pbdma_id [in,out] Pointer to store pbdma id.
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*
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* Calls function to get h/w engine id and veid for given #mmu_fault_id.
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* If h/w (active) engine id is not #INVAL_ID, call function to get pbdma id for
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* the engine having fault id as #mmu_fault_id.
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*
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* @return Updated #engine_id, #veid and #pbdma_id pointers
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*/
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void nvgpu_engine_mmu_fault_id_to_eng_ve_pbdma_id(struct gk20a *g,
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u32 mmu_fault_id, u32 *engine_id, u32 *veid, u32 *pbdma_id);
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/**
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* @brief Remove a device entry from engine list.
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*
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* @param g [in] The GPU driver struct.
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* @param dev [in] A device.
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*
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* Remove the device entry \a dev from fifo->host_engines, fifo->active_engines.
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* The device entry is retained in g->devs->devlist_heads list to ensure device
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* reset.
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*/
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void nvgpu_engine_remove_one_dev(struct nvgpu_fifo *f,
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const struct nvgpu_device *dev);
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#endif /*NVGPU_ENGINE_H*/
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