mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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9e5c88c1ef
It's preparing to add bellow CFLAGS:
-Werror -Wall -Wextra \
-Wmissing-braces -Wpointer-arith -Wundef \
-Wconversion -Wsign-conversion \
-Wformat-security \
-Wmissing-declarations -Wredundant-decls -Wimplicit-fallthrough
Jira GVSCI-11640
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I7a7afff85231aed52a20f77854c30fe5c755cae5
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2555058
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
93 lines
4.1 KiB
C
93 lines
4.1 KiB
C
/*
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* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_LOG_COMMON_H
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#define NVGPU_LOG_COMMON_H
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#include <nvgpu/bitops.h>
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enum nvgpu_log_type {
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NVGPU_ERROR = 0,
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NVGPU_WARNING,
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NVGPU_DEBUG,
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NVGPU_INFO,
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};
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/*
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* Use this define to set a default mask.
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*/
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#define NVGPU_DEFAULT_DBG_MASK U64(0)
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#define gpu_dbg_info BIT(0) /* Lightly verbose info. */
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#define gpu_dbg_fn BIT(1) /* Function name tracing. */
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#define gpu_dbg_reg BIT(2) /* Register accesses; very verbose. */
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#define gpu_dbg_pte BIT(3) /* GMMU PTEs. */
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#define gpu_dbg_intr BIT(4) /* Interrupts. */
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#define gpu_dbg_pmu BIT(5) /* gk20a pmu. */
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#define gpu_dbg_clk BIT(6) /* gk20a clk. */
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#define gpu_dbg_map BIT(7) /* Memory mappings. */
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#define gpu_dbg_map_v BIT(8) /* Verbose mem mappings. */
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#define gpu_dbg_gpu_dbg BIT(9) /* GPU debugger/profiler. */
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#define gpu_dbg_cde BIT(10) /* cde info messages. */
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#define gpu_dbg_cde_ctx BIT(11) /* cde context usage messages. */
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#define gpu_dbg_ctxsw BIT(12) /* ctxsw tracing. */
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#define gpu_dbg_sched BIT(13) /* Sched control tracing. */
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#define gpu_dbg_sema BIT(14) /* Semaphore debugging. */
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#define gpu_dbg_sema_v BIT(15) /* Verbose semaphore debugging. */
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#define gpu_dbg_pmu_pstate BIT(16) /* p state controlled by pmu. */
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#define gpu_dbg_xv BIT(17) /* XVE debugging. */
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#define gpu_dbg_shutdown BIT(18) /* GPU shutdown tracing. */
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#define gpu_dbg_kmem BIT(19) /* Kmem tracking debugging. */
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#define gpu_dbg_pd_cache BIT(20) /* PD cache traces. */
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#define gpu_dbg_alloc BIT(21) /* Allocator debugging. */
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#define gpu_dbg_dma BIT(22) /* DMA allocation prints. */
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#define gpu_dbg_sgl BIT(23) /* SGL related traces. */
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#ifdef CONFIG_NVGPU_DGPU
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#define gpu_dbg_vidmem BIT(24) /* VIDMEM tracing. */
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#endif
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#define gpu_dbg_nvlink BIT(25) /* nvlink Operation tracing. */
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#define gpu_dbg_clk_arb BIT(26) /* Clk arbiter debugging. */
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#define gpu_dbg_event BIT(27) /* Events to User debugging. */
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#define gpu_dbg_vsrv BIT(28) /* server debugging. */
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#define gpu_dbg_prof BIT(29) /* GPU profiler object debugging. */
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#define gpu_dbg_gr BIT(30) /* common.gr debugging. */
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#define gpu_dbg_mem BIT(31) /* memory accesses; very verbose. */
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#define gpu_dbg_device BIT(32) /* Device initialization and
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querying. */
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#define gpu_dbg_mig BIT(33) /* MIG info. */
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#define gpu_dbg_rec BIT(34) /* Recovery sequence debugging. */
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#define gpu_dbg_zbc BIT(35) /* Gr ZBC. */
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#define gpu_dbg_vab BIT(36) /* VAB. */
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#define gpu_dbg_runlists BIT(38) /* Runlist related debugging. */
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#define gpu_dbg_cic BIT(39) /* Interrupt Handling debugging. */
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#define gpu_dbg_falcon BIT(40) /* Falcon/NVRISCV debugging */
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#define gpu_dbg_mm BIT(41) /* Memory management debugging. */
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#define gpu_dbg_hwpm BIT(42) /* GPU HWPM. */
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#define gpu_dbg_verbose BIT(43) /* More verbose logs. */
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#define gpu_dbg_ce BIT(44) /* Copy Engine debugging */
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#ifdef CONFIG_NVS_PRESENT
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#define gpu_dbg_nvs BIT(45) /* NvGPU's NVS logging. */
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#define gpu_dbg_nvs_internal BIT(46) /* Internal NVS logging. */
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#endif
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#endif
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