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9ab1271269
It's preparing to add bellow CFLAGS:
-Werror -Wall -Wextra \
-Wmissing-braces -Wpointer-arith -Wundef \
-Wconversion -Wsign-conversion \
-Wformat-security \
-Wmissing-declarations -Wredundant-decls -Wimplicit-fallthrough
Jira GVSCI-11640
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: Ia8f508c65071aa4775d71b8ee5dbf88a33b5cbd5
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2555056
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
82 lines
2.5 KiB
C
82 lines
2.5 KiB
C
/*
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* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "acr_sw_gp10b.h"
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#include <nvgpu/types.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/pmu.h>
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#include "acr_blob_construct_v0.h"
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#include "acr_priv.h"
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#include "acr_sw_gm20b.h"
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#include "acr_sw_gp10b.h"
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/* LSF static config functions */
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static u32 gp10b_acr_lsf_gpccs(struct gk20a *g,
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struct acr_lsf_config *lsf)
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{
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(void)g;
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/* GPCCS LS falcon info */
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lsf->falcon_id = FALCON_ID_GPCCS;
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lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
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lsf->is_lazy_bootstrap = true;
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lsf->is_priv_load = true;
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lsf->get_lsf_ucode_details = nvgpu_acr_lsf_gpccs_ucode_details_v0;
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lsf->get_cmd_line_args_offset = NULL;
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return BIT32(lsf->falcon_id);
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}
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static void gp10b_acr_default_sw_init(struct gk20a *g, struct hs_acr *hs_acr)
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{
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nvgpu_log_fn(g, " ");
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/* ACR HS ucode type & f/w name*/
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hs_acr->acr_type = ACR_DEFAULT;
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if (!g->ops.pmu.is_debug_mode_enabled(g)) {
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hs_acr->acr_fw_name = HSBIN_ACR_PROD_UCODE;
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} else {
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hs_acr->acr_fw_name = HSBIN_ACR_DBG_UCODE;
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}
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/* set on which falcon ACR need to execute*/
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hs_acr->acr_flcn = g->pmu->flcn;
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hs_acr->acr_engine_bus_err_status =
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g->ops.pmu.bar0_error_status;
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}
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void nvgpu_gp10b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
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{
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nvgpu_log_fn(g, " ");
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/* inherit the gm20b config data */
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nvgpu_gm20b_acr_sw_init(g, acr);
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gp10b_acr_default_sw_init(g, &acr->acr);
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/* gp10b supports LSF gpccs bootstrap */
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acr->lsf_enable_mask |= gp10b_acr_lsf_gpccs(g,
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&acr->lsf[FALCON_ID_GPCCS]);
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}
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