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When MMU fault happens, if the id_type = 1, that means fault happened in TSG. So in that path we set the error notifier and let userspace know about faulty channel. During this, we check if debugger is attached or not by reading gr_gpc0_tpc0_sm0_dbgr_control0_r() register. During this time ELPG is enabled and this read causes IDLE SNAP error for ELPG. To resolve this, move CG/PG disable function call early in fifo recover code path. This ensures that ELPG is disabled early before any read happens for any GR register. Bug 3660592 Change-Id: Ie5d01b7ccf00167b58f260e9142aa5deb2a08be4 Signed-off-by: Divya <dsinghatwari@nvidia.com> (cherry picked from commit f09e429f2d142c20529bedc05acf193805e1bb25) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2720655 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> GVS: Gerrit_Virtual_Submit