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init_pbdma_intr_descs HAL ops is used to update the internal values of the struct intr within struct fifo_gk20a. Three kinds of intr_descriptors are filled i.e. device_fatal_0, channel_fatal_0 and restartable_0. Breaking them into separate HALs has the advantage of reusing the h/w headers corresponding to the device_fatal_0 as they are same across all the architectures while those of channel_fatal_0 varies. Another advantage is to now decouple pbdma from filling in values within the fifo_gk20a struct. A new method gk20a_fifo_init_pbdma_descs is constructed that initializes the above intr struct by calling the separate HAL ops for these. Jira NVGPU-2950 Change-Id: I78ddc61a5d9b2088d34259af90f8b85817bf19d9 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2072741 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
58 lines
2.1 KiB
C
58 lines
2.1 KiB
C
/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/types.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/hw/gp10b/hw_pbdma_gp10b.h>
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#include "pbdma_gp10b.h"
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u32 gp10b_pbdma_get_signature(struct gk20a *g)
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{
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return g->ops.get_litter_value(g, GPU_LIT_GPFIFO_CLASS)
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| pbdma_signature_sw_zero_f();
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}
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u32 gp10b_pbdma_channel_fatal_0_intr_descs(void)
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{
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/*
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* These are data parsing, framing errors or others which can be
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* recovered from with intervention... or just resetting the
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* channel
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*/
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u32 channel_fatal_0_intr_descs =
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pbdma_intr_0_gpfifo_pending_f() |
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pbdma_intr_0_gpptr_pending_f() |
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pbdma_intr_0_gpentry_pending_f() |
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pbdma_intr_0_gpcrc_pending_f() |
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pbdma_intr_0_pbptr_pending_f() |
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pbdma_intr_0_pbentry_pending_f() |
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pbdma_intr_0_pbcrc_pending_f() |
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pbdma_intr_0_method_pending_f() |
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pbdma_intr_0_methodcrc_pending_f() |
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pbdma_intr_0_pbseg_pending_f() |
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pbdma_intr_0_syncpoint_illegal_pending_f() |
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pbdma_intr_0_signature_pending_f();
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return channel_fatal_0_intr_descs;
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} |