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a22a9c2bcf
Created PMU super surface unit & moved structs/functions related to super surface under a unit, separated super surface structs into private/public based on its usage/access, made changes to supper surface dependent files to reflect supper surface changes respective to unit. JIRA NVGPU-3045 Change-Id: I6ac426052eb60f00b432d9533460aa0afd939fe3 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2088405 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
235 lines
7.4 KiB
C
235 lines
7.4 KiB
C
/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_ENABLED_H
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#define NVGPU_ENABLED_H
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struct gk20a;
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#include <nvgpu/types.h>
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/*
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* Available flags that describe what's enabled and what's not in the GPU. Each
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* flag here is defined by it's offset in a bitmap.
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*/
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#define NVGPU_IS_FMODEL 1
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#define NVGPU_DRIVER_IS_DYING 2
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#define NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP 3
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#define NVGPU_FECS_TRACE_VA 4
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#define NVGPU_CAN_RAILGATE 5
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#define NVGPU_KERNEL_IS_DYING 6
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/*
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* ECC flags
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*/
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/* SM LRF ECC is enabled */
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#define NVGPU_ECC_ENABLED_SM_LRF 8
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/* SM SHM ECC is enabled */
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#define NVGPU_ECC_ENABLED_SM_SHM 9
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/* TEX ECC is enabled */
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#define NVGPU_ECC_ENABLED_TEX 10
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/* L2 ECC is enabled */
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#define NVGPU_ECC_ENABLED_LTC 11
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/* SM L1 DATA ECC is enabled */
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#define NVGPU_ECC_ENABLED_SM_L1_DATA 12
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/* SM L1 TAG ECC is enabled */
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#define NVGPU_ECC_ENABLED_SM_L1_TAG 13
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/* SM CBU ECC is enabled */
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#define NVGPU_ECC_ENABLED_SM_CBU 14
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/* SM ICAHE ECC is enabled */
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#define NVGPU_ECC_ENABLED_SM_ICACHE 15
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/*
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* MM flags.
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*/
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#define NVGPU_MM_UNIFY_ADDRESS_SPACES 16
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/* false if vidmem aperture actually points to sysmem */
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#define NVGPU_MM_HONORS_APERTURE 17
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/* unified or split memory with separate vidmem? */
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#define NVGPU_MM_UNIFIED_MEMORY 18
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/* User-space managed address spaces support */
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#define NVGPU_SUPPORT_USERSPACE_MANAGED_AS 20
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/* IO coherence support is available */
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#define NVGPU_SUPPORT_IO_COHERENCE 21
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/* MAP_BUFFER_EX with partial mappings */
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#define NVGPU_SUPPORT_PARTIAL_MAPPINGS 22
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/* MAP_BUFFER_EX with sparse allocations */
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#define NVGPU_SUPPORT_SPARSE_ALLOCS 23
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/* Direct PTE kind control is supported (map_buffer_ex) */
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#define NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL 24
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/* Support batch mapping */
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#define NVGPU_SUPPORT_MAP_BUFFER_BATCH 25
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/* Use coherent aperture for sysmem. */
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#define NVGPU_USE_COHERENT_SYSMEM 26
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/* Use physical scatter tables instead of IOMMU */
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#define NVGPU_MM_USE_PHYSICAL_SG 27
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/* WAR for gm20b chips. */
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#define NVGPU_MM_FORCE_128K_PMU_VM 28
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/* Some chips (those that use nvlink) bypass the IOMMU on tegra. */
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#define NVGPU_MM_BYPASSES_IOMMU 29
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/*
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* Host flags
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*/
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#define NVGPU_HAS_SYNCPOINTS 30
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/* sync fence FDs are available in, e.g., submit_gpfifo */
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#define NVGPU_SUPPORT_SYNC_FENCE_FDS 31
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/* NVGPU_DBG_GPU_IOCTL_CYCLE_STATS is available */
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#define NVGPU_SUPPORT_CYCLE_STATS 32
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/* NVGPU_DBG_GPU_IOCTL_CYCLE_STATS_SNAPSHOT is available */
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#define NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT 33
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/* Both gpu driver and device support TSG */
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#define NVGPU_SUPPORT_TSG 34
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/* Fast deterministic submits with no job tracking are supported */
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#define NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING 35
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/* Deterministic submits are supported even with job tracking */
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#define NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_FULL 36
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/* NVGPU_IOCTL_CHANNEL_RESCHEDULE_RUNLIST is available */
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#define NVGPU_SUPPORT_RESCHEDULE_RUNLIST 37
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/* NVGPU_GPU_IOCTL_GET_EVENT_FD is available */
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#define NVGPU_SUPPORT_DEVICE_EVENTS 38
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/* FECS context switch tracing is available */
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#define NVGPU_SUPPORT_FECS_CTXSW_TRACE 39
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/* NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS is available */
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#define NVGPU_SUPPORT_DETERMINISTIC_OPTS 40
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/*
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* Security flags
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*/
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#define NVGPU_SEC_SECUREGPCCS 41
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#define NVGPU_SEC_PRIVSECURITY 42
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/* VPR is supported */
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#define NVGPU_SUPPORT_VPR 43
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/*
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* Nvlink flags
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*/
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#define NVGPU_SUPPORT_NVLINK 45
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/*
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* PMU flags.
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*/
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/* perfmon enabled or disabled for PMU */
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#define NVGPU_PMU_PERFMON 48
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#define NVGPU_PMU_PSTATE 49
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#define NVGPU_PMU_ZBC_SAVE 50
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#define NVGPU_PMU_FECS_BOOTSTRAP_DONE 51
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#define NVGPU_GPU_CAN_BLCG 52
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#define NVGPU_GPU_CAN_SLCG 53
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#define NVGPU_GPU_CAN_ELCG 54
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/* Clock control support */
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#define NVGPU_SUPPORT_CLOCK_CONTROLS 55
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/* NVGPU_GPU_IOCTL_GET_VOLTAGE is available */
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#define NVGPU_SUPPORT_GET_VOLTAGE 56
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/* NVGPU_GPU_IOCTL_GET_CURRENT is available */
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#define NVGPU_SUPPORT_GET_CURRENT 57
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/* NVGPU_GPU_IOCTL_GET_POWER is available */
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#define NVGPU_SUPPORT_GET_POWER 58
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/* NVGPU_GPU_IOCTL_GET_TEMPERATURE is available */
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#define NVGPU_SUPPORT_GET_TEMPERATURE 59
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/* NVGPU_GPU_IOCTL_SET_THERM_ALERT_LIMIT is available */
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#define NVGPU_SUPPORT_SET_THERM_ALERT_LIMIT 60
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/* whether to run PREOS binary on dGPUs */
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#define NVGPU_PMU_RUN_PREOS 61
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/* set if ASPM is enabled; only makes sense for PCI */
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#define NVGPU_SUPPORT_ASPM 62
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/* subcontexts are available */
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#define NVGPU_SUPPORT_TSG_SUBCONTEXTS 63
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/* Simultaneous Compute and Graphics (SCG) is available */
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#define NVGPU_SUPPORT_SCG 64
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/* GPU_VA address of a syncpoint is supported */
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#define NVGPU_SUPPORT_SYNCPOINT_ADDRESS 65
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/* Allocating per-channel syncpoint in user space is supported */
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#define NVGPU_SUPPORT_USER_SYNCPOINT 66
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/* USERMODE enable bit */
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#define NVGPU_SUPPORT_USERMODE_SUBMIT 67
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/* Multiple WPR support */
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#define NVGPU_SUPPORT_MULTIPLE_WPR 68
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/* SEC2 RTOS support*/
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#define NVGPU_SUPPORT_SEC2_RTOS 69
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/* PMU RTOS FBQ support*/
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#define NVGPU_SUPPORT_PMU_RTOS_FBQ 70
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/* ZBC STENCIL support*/
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#define NVGPU_SUPPORT_ZBC_STENCIL 71
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/* PLATFORM_ATOMIC support */
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#define NVGPU_SUPPORT_PLATFORM_ATOMIC 72
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/* SEC2 VM support */
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#define NVGPU_SUPPORT_SEC2_VM 73
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/* GSP VM support */
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#define NVGPU_SUPPORT_GSP_VM 74
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/* GFXP preemption support */
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#define NVGPU_SUPPORT_PREEMPTION_GFXP 75
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/* PMU Super surface */
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#define NVGPU_SUPPORT_PMU_SUPER_SURFACE 76
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/*
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* Must be greater than the largest bit offset in the above list.
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*/
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#define NVGPU_MAX_ENABLED_BITS 77U
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/**
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* nvgpu_is_enabled - Check if the passed flag is enabled.
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*
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* @g - The GPU.
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* @flag - Which flag to check.
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*
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* Returns true if the passed @flag is true; false otherwise.
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*/
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bool nvgpu_is_enabled(struct gk20a *g, int flag);
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/**
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* nvgpu_set_enabled - Set the state of a flag.
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*
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* @g - The GPU.
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* @flag - Which flag to modify.
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* @state - The state to set the flag to.
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*
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* Set the state of the passed @flag to @state.
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*
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* This is generally a somewhat low level operation with lots of potential
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* side effects. Be weary about where and when you use this. Typically a bunch
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* of calls to this early in the driver boot sequence makes sense (as
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* information is determined about the GPU at run time). Calling this in steady
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* state operation is probably an incorrect thing to do.
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*/
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void nvgpu_set_enabled(struct gk20a *g, int flag, bool state);
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int nvgpu_init_enabled_flags(struct gk20a *g);
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void nvgpu_free_enabled_flags(struct gk20a *g);
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#endif /* NVGPU_ENABLED_H */
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